Epson technical manual MC68328 To S1D13705 Interface, Hardware Description

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2.4 MC68328 To S1D13705 Interface

2.4.1 Hardware Description

The interface between the MC68328 and the S1D13705 can be implemented using either the MC68K #1 or Generic #1 host bus interface of the S1D13705.

Using The MC68K #1 Host Bus Interface

The MC68328 multiplexes dual functions on some of its bus control pins (specifically UDS, LDS, and DTACK). In implementations where all of these pins are available for use as bus control pins, then the S1D13705 interface is a straightforward implementation of the “MC68K #1” host bus interface.

The following diagram shows a typical implementation of the MC68328 to S1D13705 using the MC68K #1 host bus interface. For further information on the MC68K #1 host bus interface and AC Timing, refer to the S1D13705 Hardware Functional Specification, document number X27A-A-001-xx.

MC68328

A[16:0]

D[15:0]

CSB3

DTACK

AS

UDS

LDS

R/W

CLK0

Vcc

1K

Vcc

Vcc

S1D13705

AB[16:1]

DB[15:0]

CS#

WAIT#

BS#

WE1#

AB0

RD/WR#

RD#

WE0##

BUSCLK

System RESET

RESET#

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 2-1: Typical Implementation of MC68328 to S1D13705 Interface - MC68K #1

S1D13705	Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
X27A-G-007-04	Issue Date: 01/02/13