Epson technical manual Bit Processor to S1D13705 Interface, Hardware Description

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4 8-Bit Processor to S1D13705 Interface

4.1 Hardware Description

The interface between the S1D13705 and an 8-bit processor requires minimal glue logic. A decoder is used to generate the chip select for the S1D13705 based on where the S1D13705 is mapped into memory. Alternatively, if the processor supports a chip select module, it can be programmed to generate a chip select for the S1D13705 without the need of an address decoder.

An inverter inverts A0 to generate the Byte High Enable signal for the S1D13705. If the 8-bit host interface has an active high WAIT signal, it must be inverted as well.

In order to support an 8-bit microprocessor with a 16-bit peripheral, the low and high order bytes of the data bus must be connected together. The following diagram shows a typical implementation of an 8-bit processor interfaced to the S1D13705.

Generic 8-bit Bus		S1D13705
A[0]		AB[0]
A[16:1]		AB[16:1]
D[7:0]		DB[7:0]
		DB[15:8]
	Decoder	CS#
WAIT#		WAIT#
WE#		WE0#
RD#		RD#
		BHE# (WE1#)
		IO VDD
		RD/WR#
		BS#
BUSCLK		BUSCLK
	System RESET	RESET#

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of an 8-bit Processor to the S1D13705 Generic #2 Interface

Interfacing to an 8-bit Processor	S1D13705
Issue Date: 01/12/20	X27A-G-015-01