Epson S1D13705 technical manual CPU Module Description, Clock Signals Busclk, Clki

Page 12	EPSON Research and Development
	Vancouver Design Center

4 CPU Module Description

This section will describe the various parts of the CPU module that pertain to the

S1D13704/5 LCD Controller.

4.1 Clock Signals

4.1.1 BUSCLK

Because the bus clock for the S1D13704/5 does not need to be synchronous with the bus interface control signals, a lot of flexibility is available in the choice for BUSCLK. In this CPU module, BUSCLK is a divided by two version of the SDRAM clock signal, DCLKOUT. Since DCLKOUT equals 73.728MHz, BUSCLK = 36.864MHz.

4.1.2 CLKI

The pixel clock for the S1D13704/5, CLKI, is also asynchronous with respect to the interface control signals. This clock is selected based upon panel frame rates, power vs performance budget, and maximum input frequencies. The maximum CLKI input is 25MHz if the internal CLKI/2 isn’t used, and if it is used the maximum input is 50MHz.

On the CPU module, CLKI’s default input is a divided by four version of DCLKOUT, which gives a CLKI = 18.432MHZ. This frequency gives good performance for 320x240 resolution panels for both portrait and landscape modes. If power saving is desired, the CLKI can be reduced by using the internal CLKI/2 and the various PCLK and MCLK dividers for portrait mode.

A socket for an external oscillator is also provided if a different frequency is required. This option is selected by positioning jumper JP8 in the 2 3 position and adding a standard 14- DIP type oscillator in the socket U10.

4.2 LCD Connectors

4.2.1 50-pin LCD Module Connector, J3

The standard connector used on Toshiba’s CPU Modules to connect to the LCD module is included in this CPU module. All twelve LCD data lines, FPDAT[11:0], from the S1D13704/5, as well as the five video control signals, FPFRAME, FPSHIFT, FPLINE, DRDY, LCDPWR, are passed through this connector. Through this connector, the S1D13704/5 supports monochrome and color STN panels up to a resolution of 640x480 as well as color TFT/D-TFT up to a resolution of 640x480. All touch panel signals from the main board have also been routed through this connector.

	S5U13704/5 - TMPR3912/22U CPU Module
X00A-G-004-02	Issue Date: 01/03/07