Epson S1D13705 technical manual Generic #2 Interface Timing, Generic #2 Timing

Epson Research and Development Page 33

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7.1.6 Generic #2 Interface Timing

	TBCLK
BCLK
A[16:0]		VALID
BHE#
CS#
	t1			t2
WE#,RD#
	t3			t4
	Hi-Z	VALID
D[15:0]
(write)	t5			t7
		t6
	Hi-Z		VALID	Hi-Z
D[15:0]
(read)		t9		t10
	t8
WAIT#	Hi-Z		t11	Hi-Z
		Figure 7-6: Generic #2 Timing

Table 7-6: Generic #2 Timing

Symbol	Parameter	Min	Max	Units
fBCLK	Bus Clock frequency		50	MHz
TBCLK	Bus Clock period	1/fBCLK
t1	A[16:0], BHE#, CS# valid to WE#, RD# low	0		ns
t2	WE#, RD# high to A[16:0], BHE#, CS# invalid	0		ns
t3	WE# low to D[15:0] valid (write cycle)		TBCLK
t4	WE# high to D[15:0] invalid (write cycle)	0		ns
t5	RD# low to D[15:0] driven (read cycle)		16	ns
t6	D[15:0] valid to WAIT# high (read cycle)	0		ns
t7	RD# high to D[15:0] high impedance (read cycle)		10	ns
t8	WE#, RD# low to WAIT# driven low		14	ns
t9	BCLK to WAIT# high		10	ns
t10	WE#, RD# high to WAIT# high impedance		11	ns
t11	WAIT# high to WE#, RD# high	1TBCLK

Note

BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 84

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10