Epson S1D13705 technical manual MCF5307 Memory Read Cycle

Epson Research and Development	Page 9
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BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]			Sampled when TA low
Transfer Start	Wait States	Transfer	Next Transfer
		Complete	Starts

Figure 2-1: MCF5307 Memory Read Cycle

BCLK0

TS

TA

TIP

A[31:0]

R/W

SIZ[1:0], TT[1:0]

D[31:0] Valid

Transfer Start	Wait States	Transfer	Next Transfer
		Complete	Starts

Figure 2-2: MCF5307 Memory Write Cycle

2.1.3 Burst Cycles

Burst cycles are very similar to normal cycles, except that they occur as a series of four back-to-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted continuously through the burst. Burst memory cycles are mainly intended to facil- itate cache line fill from program or data memory; they are typically not used for transfers to or from IO peripheral devices such as the S1D13705. The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them.

Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor	S1D13705
Issue Date: 01/02/13	X27A-G-011-02