Epson Research and Development

Page 31

Vancouver Design Center

7.1.4 Motorola MC68K #2 Interface Timing

 

TCLK

 

 

CLK

 

 

 

A[16:0]

 

 

 

CS#

 

VALID

 

SIZ0, SIZ1

 

 

 

R/W#

t1

 

t2

 

 

AS#

 

 

 

DS#

 

 

 

 

t3

t5

t7

 

 

 

 

t4

t6

DSACK1#

Hi-Z

 

Hi-Z

 

 

 

 

t8

 

t9

 

 

 

D[31:16]

Hi-Z

VALID

Hi-Z

(write)

 

 

 

 

 

 

t10

 

t11

D[31:16]

Hi-Z

VALID

Hi-Z

(read)

 

 

 

 

 

 

Figure 7-4: MC68K #2 Timing (MC68030)

 

Table 7-4: MC68K #2 Timing (MC68030)

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

fCLK

Bus Clock frequency

 

33

MHz

TCLK

Bus Clock period

1/fCLK

 

 

t1

A[16:0], CS#, SIZ0, SIZ1 valid before AS# falling edge

0

 

ns

 

 

 

 

 

t2

A[16:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge

0

 

ns

 

 

 

 

 

t3

AS# low to DSACK1# driven high

 

22

ns

 

 

 

 

 

t4

CLK to DSACK1# low

 

18

ns

 

 

 

 

 

t5

CLK to AS#, DS# high

1TCLK

 

ns

t6

AS# high to DSACK1# high

 

20

ns

 

 

 

 

 

t7

AS# high to DSACK1# high impedance

 

TCLK

 

t8

DS# falling edge to D[31:16] valid (write cycle)

 

TCLK/2

 

t9

AS#, DS# rising edge to D[31:16] invalid (write cycle)

0

 

ns

 

 

 

 

 

t10

D[31:16] valid to DSACK1# low (read cycle)

0

 

ns

 

 

 

 

 

t11

AS#, DS# rising edge to D[31:16] high impedance

 

20

ns

 

 

 

 

 

Note

CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off

BCLK Between Accesses” on page 84

Hardware Functional Specification

S1D13705

Issue Date: 02/02/01

X27A-A-001-10

Page 37
Image 37
Epson S1D13705 Motorola MC68K #2 Interface Timing, AS# high to DSACK1# high AS# high to DSACK1# high impedance