Epson S1D13705 Power Down/Up Timing, Lcdpwr Override REG03h bit HW Power Save, Active Inactive

Epson Research and Development	Page 37
Vancouver Design Center

7.3.2 Power Down/Up Timing

LCDPWR Override (REG[03h] bit 3)

HW Power Save
or
Software Power Save	11	00
REG[03h] bits [1:0]
FP Signals	Active		Inactive
			t4
LCDPWR	t3

11

Active

t5 t6

00

t1 t2

Inactive

11

Active

t7

Figure 7-10: Power Down/Up Timing

Table 7-10: Power Down/Up Timing

Symbol	Parameter	Min	Typ	Max	Units
t1	HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY			1	Frame
	inactive - LCDPWR Override = 1
t2	HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY			1	Frame
	active - LCDPWR Override = 1
t3	HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY			1	Frame
	inactive - LCDPWR Override = 0
t4	LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive		127		Frame
	- LCDPWR Override = 0
t5	HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,		0		Frame
	LCDPWR active - LCDPWR Override = 0
t6	LCDPWR Override active (1) to LCDPWR inactive			1	Frame
t7	LCDPWR Override inactive (1) to LCDPWR active			1	Frame

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10