Epson S1D13705 10 9/12-Bit TFT/D-TFD Panel Timing, 25 12-Bit TFT/D-TFD Panel Timing

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7.3.10 9/12-Bit TFT/D-TFD Panel Timing

VNDP2

VDPVNDP1

FPFRAME

FPLINE

FPDAT[11:0] LINE480

DRDY

FPLINE

HNDP2

FPSHIFT

DRDY

FPDAT[9]

FPDAT[2:0]

FPDAT[10]

FPDAT[4:3]

FPDAT[11]

FPDAT[8:6]

LINE1 LINE480

HDPHNDP1

1-1 1-2 1-640

1-1 1-2 1-640

1-1 1-2 1-640

Note: DRDY is used to indicate the first pixel

Example Timing for 12-bit 640x480 panel

Figure 7-25: 12-Bit TFT/D-TFD Panel Timing

VDP =	Vertical Display Period	= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
VNDP =	Vertical Non-Display Period	= VNDP1 + VNDP2 = (REG[0Ah] bits 5-0) Lines
VNDP1 =	Vertical Non-Display Period 1	= REG[09h] bits 5-0 Lines
VNDP2 =	Vertical Non-Display Period 2	= (REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines
HDP =	Horizontal Display Period	= ((REG[04h] bits 6-0) + 1) x 8Ts
HNDP =	Horizontal Non-Display Period	= HNDP1 + HNDP2 = (REG[08h] + 4) x 8Ts
HNDP1=	Horizontal Non-Display Period 1	= ((REG[07h] bits4-0) x 8) +16Ts
HNDP2=	Horizontal Non-Display Period 2	= (((REG[08h] bits4-0) - (REG[07h] bits 4-0)) x 8) +16Ts

S1D13705	Hardware Functional Specification
X27A-A-001-10	Issue Date: 02/02/01