Epson Research and Development

Page 57

Vancouver Design Center

 

 

 

REG[02h] Mode Register 1

 

 

 

 

 

 

Address = 1FFE2h

 

 

 

 

 

Read/Write.

 

 

 

 

 

 

 

 

 

Bit-Per-Pixel

Bit-Per-Pixel

 

High

Input Clock

 

Frame

Hardware

Software

 

divide

Display Blank

Video Invert

Bit 1

Bit 0

 

Performance

Repeat

Video Invert

 

(CLKI/2)

 

Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 7-6

Bit-Per-Pixel Bits [1:0]

 

 

 

 

These bits select the color or gray-scale depth (Display Mode).

 

 

 

 

Table 8-2: Gray Scale/Color Mode Selection

 

 

 

 

 

 

 

 

 

 

Color/Mono

Bit-Per-Pixel Bit 1

Bit-Per-Pixel Bit 0

Display Mode

 

 

REG[01h] bit 5

REG[02h] bit 7

REG[02h] bit 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

2 Gray scale

1 bit-per-pixel

 

 

 

 

 

 

 

 

0

1

4 Gray scale

2 bit-per-pixel

 

 

 

 

 

 

 

 

 

 

 

1

0

16 Gray scale

4 bit-per-pixel

 

 

 

 

 

 

 

 

 

 

 

 

1

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

2 Colors

1 bit-per-pixel

 

 

 

 

 

 

 

 

1

1

4 Colors

2 bit-per-pixel

 

 

 

 

 

 

 

 

 

 

 

1

0

16 Colors

4 bit-per-pixel

 

 

 

 

 

 

 

 

 

 

 

 

1

256 Colors

8 bit-per-pixel

 

 

 

 

 

 

 

 

 

 

 

bit 5

High Performance (Landscape Modes Only)

 

 

 

When this bit = 0, the internal Memory Clock (MCLK) is a divided-down version of the

 

Pixel Clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the

 

table below.

 

 

 

 

Table 8-3: High Performance Selection

High Performance

BPP Bit 1

BPP Bit 0

Display Modes

 

 

 

 

 

 

0

0

MClk = PClk/8

1 bit-per-pixel

 

 

 

 

0

1

MClk = PClk/4

2 bit-per-pixel

 

 

 

 

 

1

0

MClk = PClk/2

4 bit-per-pixel

 

 

 

 

 

 

1

MClk = PClk

8 bit-per-pixel

 

 

 

 

 

 

 

1

X

X

MClk = PClk

 

 

 

 

 

When this bit = 1, MCLK is fixed to the same frequency as PCLK for all bit-per-pixel modes. This provides a faster screen update performance in 1/2/4 bit-per-pixel modes, but also increases power consumption. This bit can be set to 1 just before a major screen update, then set back to 0 to save power after the update. This bit has no effect in Swivel- View mode. Refer to REG[1Bh] SwivelView Mode Register on page 67 for SwivelView mode clock selection.

Hardware Functional Specification

S1D13705

Issue Date: 02/02/01

X27A-A-001-10

Page 63
Image 63
Epson S1D13705 Gray Scale/Color Mode Selection, High Performance Selection, Color/Mono Bit-Per-Pixel Bit Display Mode