Epson S1D13705 technical manual = REG08h bits 4-0 x 2x 8 + 17Ts

Epson Research and Development	Page 51
Vancouver Design Center

Sync Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Data Timing

Line Pulse

Shift Pulse

FPDAT[7:0]

t1	t2
t4	t3

t5

t6

		t8					t9
t7	t14					t11		t10
				t12	t13
			1				2

Figure 7-24: Dual Color 8-Bit Panel A.C. Timing

Table 7-17: Dual Color 8-Bit Panel A.C. Timing

Symbol		Parameter	Min	Typ	Max	Units
	t1	Frame Pulse setup to Line Pulse falling edge	note 2			(note 1)
	t2	Frame Pulse hold from Line Pulse falling edge	9			Ts
	t3	Line Pulse period	note 3
	t4	Line Pulse pulse width	9			Ts
	t5	MOD delay from Line Pulse falling edge	1			Ts
	t6	Shift Pulse falling edge to Line Pulse rising edge	note 5
	t7	Shift Pulse falling edge to Line Pulse falling edge	note 6
	t8	Line Pulse falling edge to Shift Pulse falling edge	t14 + 1			Ts
	t9	Shift Pulse period	2			Ts
	t10	Shift Pulse pulse width low	1			Ts
	t11	Shift Pulse pulse width high	1			Ts
	t12	FPDAT[7:0] setup to Shift Pulse falling edge	1			Ts
	t13	FPDAT[7:0] hold to Shift Pulse falling edge	1			Ts
	t14	Line Pulse falling edge to Shift Pulse rising edge	39			Ts
1.	Ts	= pixel clock period
2.	t1min	= t3min - 9Ts
3.	t3min	= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts
5.	t6min	= [((REG[08h] bits 4-0) x 2)x 8 + 17]Ts
6.	t7min	= [((REG[08h] bits 4-0) x 2)x 8 + 26]Ts

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10