Epson S1D13705 technical manual Pclk

Epson Research and Development	Page 71
Vancouver Design Center

**Register 07h - FPLINE Start Position - not used by STN

*/

SET_REG(0x07, 0x00); /*

**Register 08h - Horizontal Non-Display Period = (Reg[08] + 4) * 8

**	=	(0+4) *	8 = 32 pels
**	- HNDP and VNDP are calculated to	achieve	the
**	desired frame rate according to:
**
**	PCLK
**	Frame Rate = ---------------------------
**	(HDP + HNDP) * (VDP	+ VNDP)
*/

SET_REG(0x08, 0x00); /*

**Register 09h - FPFRAME Start Position - not used by STN

*/

SET_REG(0x09, 0x00); /*

**Register 0Ah - Vertical Non-Display Register = 3 lines

**	- Calculated in conjunction	with register 08h (HNDP) to
**	achieve the desired frame	rate.
*/

SET_REG(0x0A, 0x03); /*

**Register 0Bh - MOD Rate - not used by this panel

*/

SET_REG(0x0B, 0x00); /*

**Register 0Ch - Screen 1 Start Word Address LSB

**Register 0Dh - Screen 1 Start Word Address MSB

**	- Start address should be set to 0
*/

SET_REG(0x0C, 0x00); SET_REG(0x0D, 0x00); /*

**Register 0Eh - Screen 2 Start Word Address LSB

**Register 0Fh - Screen 2 Start Word Address MSB

**- Set this start address to 0 too

*/

SET_REG(0x0E, 0x00);

SET_REG(0x0F, 0x00);

SET_REG(0x10, 0x00); /* Screen1/Screen2 Start Address High bits. */ /*

** Register 11h - Memory Address Offset

**	- Used for setting memory to a		width greater than the
**	display size. Usually set	to	0 during initialization
**	and programmed to desired	value later.
*/

Programming Notes and Examples	S1D13705
Issue Date: 02/01/22	X27A-G-002-03