Epson technical manual S1D13705 to TMPR3912 Connection Using an IT8368E

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				S1D13705
TMPR3912			+3.3V	IO VDD, CORE VDD
A[12:0]				AB[12:0]
ENDIAN				AB[16:13]
D[31:24]				DB[7:0]
D[23:16]				DB[16:8]
	VDD	pull-up	System RESET	RESET#
CARDxWAIT*				WAIT#
DCLKOUT			See text	CLKI
			...or...
IT8368E	Clock divider			BCLK
			Oscillator
LHA[23]/MFIO[10]				WE1#
LHA[22]/MFIO[9]				WE0#
LHA[21]/MFIO[8]				RD/WR#
LHA[20]/MFIO[7]				RD#
LHA[19]/MFIO[6]				CS#
LHA[16:13]/				BS#
MFIO[3:0]

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 5-1: S1D13705 to TMPR3912 Connection Using an IT8368E

Note

See Section 3.1 on page 9 and Section 3.2 on page 10 for Generic #1 pin descriptions.

The “Generic #1” host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and whether to use DCLKOUT (divided) as clock source, should be based on pixel and frame rates, power budget, part count and maximum S1D13705 respective clock frequencies. Also, internal S1D13705 clock dividers provide additional flexibility.

Interfacing to the Toshiba MIPS TMPR3912 Microprocessor	S1D13705
Issue Date: 01/02/13	X27A-G-004-02