Epson S1D13705 technical manual Generic #2 Interface Mode

Page 10	Epson Research and Development
	Vancouver Design Center

3.2 Generic #2 Interface Mode

Generic #2 Host Bus Interface is a general, non-processor specific interface mode on the S1D13705 that is ideally suited to interface to an 8-bit processor bus.

The interface requires the following signals:

•BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. If the host CPU bus does not provide this clock, an asynchronous clock can be provided.

•The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect directly to the CPU address and data bus, respectively.

Note

In an 8-bit environment D[7:0] must also be connected to DB[15:8] respectively (i.e. D7 connects to both DB15 and DB7, D6 connects to both DB14 and DB6, D5 connects to both DB13 and DB5, etc.). See Figure 4-1: “Typical Implementation of an 8-bit Proces- sor to the S1D13705 Generic #2 Interface” .

•Chip Select (CS#) is driven by decoding the high-order address lines to select the proper memory address space.

•BHE# (WE1#) is the high byte enable for both read and write cycles.

Note

In an 8-bit environment, this signal is driven by inverting address line A0 thus indicating that odd addresses are to be R/W on the high byte of the data bus.

•WE0# is the enable signal for a write access, to be driven low when the host CPU is writing the 1375 memory or registers.

•RD# is the read enable for the S1D13705, to be driven low when the host CPU is reading data from the S1D13705.

•WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the S1D13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the 1375 internal registers and/or refresh memory. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. This signal is active low and may need to be inverted if the host CPU wait state signal is active high.

•The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter- face for Generic #2 mode. However, BS# is used to configure the S1D13705 for

Generic #2 mode and should be tied high (connected to IO VDD). RD/WR# should also be tied high.

S1D13705	Interfacing to an 8-bit Processor
X27A-G-015-01	Issue Date: 01/12/20