Epson Research and Development

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REG[07h] FPLINE Start Position

 

 

 

 

 

 

Address = 1FFE7h

 

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

n/a

 

n/a

 

n/a

FPLINE Start

 

FPLINE Start

FPLINE Start

FPLINE Start

FPLINE Start

 

 

Position Bit 4

 

Position Bit 3

Position Bit 2

Position Bit 1

Position Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 4-0

 

FPLINE Start Position

 

 

 

 

 

 

 

 

These bits are used in TFT/D-TFD mode to specify the position of the FPLINE pulse.

 

 

 

These bits specify the delay, in 8-pixel resolution, from the end of a line of display data

 

 

 

(FPDAT) to the leading edge of FPLINE. This register is effective in TFT/D-TFD mode

 

 

 

only (REG[01h] bit 7 = 1). This register is programmed as follows:

 

 

 

 

 

FPLINEposition(pixels)

 

= (REG[07h] + 2) ⋅ 8

 

 

 

 

 

The following constraint must be satisfied:

 

 

 

 

 

 

 

 

REG[07h] ≤

REG[08h]

 

 

 

 

 

 

 

 

 

REG[08h] Horizontal Non-Display Period

 

 

 

 

 

Address = 1FFE8h

 

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Horizontal

 

Horizontal

Horizontal

Horizontal

Horizontal

n/a

 

n/a

 

n/a

Non-Display

 

Non-Display

Non-Display

Non-Display

Non-Display

 

 

 

 

 

Period Bit 4

 

Period Bit 3

Period Bit 2

Period Bit 1

Period Bit 0

 

 

 

 

 

 

 

 

 

 

 

bits 4-0

 

Horizontal Non-Display Period

 

 

 

 

 

These bits specify the horizontal non-display period in 8-pixel resolution.

HorizontalNonDisplayPeriod(pixels) = (REG[08h] + 4 ) ⋅ 8

REG[09h] FPFRAME Start Position

 

 

 

 

 

Address = 1FFE9h

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPFRAME

FPFRAME

FPFRAME

FPFRAME

FPFRAME

FPFRAME

n/a

 

n/a

 

Start Position

Start Position

Start Position

Start Position

Start Position

Start Position

 

 

 

 

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

 

bits 5-0

 

FPFRAME Start Position

 

 

 

 

 

 

 

These bits are used in TFT/D-TFD mode to specify the position of the FPFRAME pulse.

These bits specify the number of lines between the last line of display data (FPDAT) and the leading edge of FPFRAME. This register is effective in TFT/D-TFD mode only (REG[01h] bit 7 = 1). This register is programmed as follows:

FPFRAMEposition(lines)= REG[09h]

The contents of this register must be greater than zero and less than or equal to the Vertical Non-Display Period Register, i.e.

1 REG[09h ]≤ REG[0Ah]Bits 5:0

Hardware Functional Specification

S1D13705

Issue Date: 02/02/01

X27A-A-001-10

Page 67
Image 67
Epson S1D13705 technical manual Following constraint must be satisfied, Fpline Start