Epson S1D13705 technical manual Input Clock Frequency Bclk MHz, Input Clock period Bclk

Epson Research and Development	Page 35
Vancouver Design Center

Clock Input Waveform

tPWH	tPWL
90%
VIH
VIL
10%
tr	t f
	TBCLK

Figure 7-8: Clock Input Requirements for BCLK

Table 7-8: Clock Input Requirements for BCLK

Symbol	Parameter	Min	Max	Units
fBCLK	Input Clock Frequency (BCLK)		50	MHz
TBCLK	Input Clock period (BCLK)	1/fCLKI
tPWH	Input Clock Pulse Width High (BCLK)	8		ns
tPWL	Input Clock Pulse Width Low (BCLK)	8		ns
tf	Input Clock Fall Time (10% - 90%)		5	ns
tr	Input Clock Rise Time (10% - 90%)		5	ns

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10