Epson S1D13705 Figure 7-8: Clock Input Requirements for BCLK Table 7-8: Clock Input Requirements for BCLK

Epson Research and Development Page 35
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Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
Figure 7-8: Clock Input Requirements for BCLK
Table 7-8: Clock Input Requirements for BCLK
Symbol Parameter Min Max Units
fBCLK Input Clock Frequency (BCLK) 50 MHz
TBCLK Input Clock period (BCLK) 1/fCLKI
tPWH Input Clock Pulse Width High (BCLK) 8 ns
tPWL Input Clock Pulse Width Low (BCLK) 8 ns
tfInput Clock Fall Time (10% - 90%) 5 ns
trInput Clock Rise Time (10% - 90%) 5 ns
tPWL tPWH
tf
Clock Input Waveform
tr
TBCLK
VIH
VIL
10%
90%