Epson S1D13705 technical manual Sync Timing, Data Timing

Epson Research and Development	Page 39
Vancouver Design Center

Sync Timing

Frame Pulse

Line Pulse

DRDY (MOD)

t1

t4

t5

t2

t3

Data Timing

Line Pulse

t6

t7

Shift Pulse

FPDAT[7:4]

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

t8

t14

t12 t13

1

t9

t11 t10

2

Figure 7-12: Single Monochrome 4-Bit Panel A.C. Timing

Table 7-11: Single Monochrome 4-Bit Panel A.C. Timing

	Symbol		Parameter	Min	Typ	Max	Units
	t1		Frame Pulse setup to Line Pulse falling edge	note 2			(note 1)
	t2		Frame Pulse hold from Line Pulse falling edge	9			Ts
	t3		Line Pulse period	note 3
	t4		Line Pulse pulse width	9			Ts
	t5		MOD delay from Line Pulse rising edge	1			Ts
	t6		Shift Pulse falling edge to Line Pulse rising edge	note 4
	t7		Shift Pulse falling edge to Line Pulse falling edge	note 5
	t8		Line Pulse falling edge to Shift Pulse falling edge	t14 + 2			Ts
	t9		Shift Pulse period	4			Ts
	t10		Shift Pulse pulse width low	2			Ts
	t11		Shift Pulse pulse width high	2			Ts
	t12		FPDAT[7:4] setup to Shift Pulse falling edge	2			Ts
	t13		FPDAT[7:4] hold to Shift Pulse falling edge	2			Ts
	t14		Line Pulse falling edge to Shift Pulse rising edge	23			Ts
1.	Ts	= pixel clock period
2.	t1min	= t3min - 9Ts
3.	t3min	= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
4.	t6min	= [(REG[08h] bits 4-0) x 8 + 2]Ts
5.	t7min	= [(REG[08h] bits 4-0) x 8 + 11]Ts

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10