Schematic Diagrams | Epson S1D13705 specs

X27A-G-005	S1D13705
-03

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3

4	5	6	7	8
			IOVDD

8

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S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board Issue Date:

Figure 8-1: S1D13705B00C Schematic Diagram (1 of 4)

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C

D

JP1

3	3.3V
2	IOVDD
1	VCC

HEADER 3

1 2 5.0V IOVDD

2 3 3.3V IOVDD

								U1
SA[0..19]	SA[0..19]
SA[0..19]
					SA0		70		AB0
					SA1		69		AB0
					SA1		69		AB1
					SA2		68		AB1
					SA2		68		AB2
					SA3		67		AB2
					SA3		67		AB3
					SA4		66		AB3
					SA4		66		AB4
					SA5		65		AB4
					SA5		65		AB5
					SA6		64		AB5
					SA6		64		AB6
					SA7		63		AB6
					SA7		63		AB7
					SA8		62		AB7
					SA8		62		AB8
					SA9		59		AB8
									AB9

					SA10		58
					SA10		58		AB10
					SA11		57		AB10
					SA11		57		AB11
					SA12		56		AB11
					SA12		56		AB12
					SA13		55		AB12
					SA13		55		AB13
					SA14		54		AB13
					SA14		54		AB14
					SA15		53		AB14
					SA15		53		AB15
					SA16		45		AB15
					SA16		45		AB16
SD[0..15]	SD[0..15]								AB16
	SD[0..15]

					SD0		19		DB0
					SD1		18		DB0
					SD1		18		DB1
					SD2		17		DB1
					SD2		17		DB2
					SD3		16		DB2
					SD3		16		DB3
					SD4		15		DB3
					SD4		15		DB4
					SD5		14		DB4
					SD5		14		DB5
					SD6		13		DB5
					SD6		13		DB6
					SD7		12		DB6
					SD7		12		DB7
					SD8		11		DB7
					SD8		11		DB8
					SD9		9		DB8
					SD9		9		DB9
					SD10		8		DB9
					SD10		8		DB10
					SD11		7		DB10
					SD11		7		DB11
					SD12		6		DB11
					SD12		6		DB12
					SD13		5		DB12
					SD13		5		DB13
					SD14		4		DB13
					SD14		4		DB14
					SD15		3		DB14
					SD15		3		DB15
RD/WR#							79		DB15
							79		RD/WR#
							78		RD/WR#
WE1#							78		WE1#
WE1#							77		WE1#
WE0#							77		WE0#
WE0#							76		WE0#
RD#							76		RD#
RD#							75		RD#
BS#							75		BS#
BS#							73		BS#
RESET#							73		RESET#
RESET#							74		RESET#
CS#							74		CS#
CS#							71		CS#
BUSCLK							71		BCLK
BUSCLK							51		BCLK
CLKI							51		CLKI
CLKI							2		CLKI
WAIT#							2		WAIT#
WAIT#							44		WAIT#
							44		TESTEN

By-pass Capacitors (1 per power pin)

	3.3V					1	COREVDD
	3.3V	C1	C2	C3	C4	21	COREVDD
						21	COREVDD
						41	COREVDD
		0.1uF	0.1uF	0.1uF	0.1uF	41	COREVDD
		0.1uF	0.1uF	0.1uF	0.1uF	61	COREVDD
						61	COREVDD
							COREVDD
	IOVDD					10	IOVDD
		C5	C6	C7		29	IOVDD
						29	IOVDD
						52	IOVDD
		0.1uF	0.1uF	0.1uF		52	IOVDD
		0.1uF	0.1uF	0.1uF			IOVDD
						20	VSS
						27	VSS
						27	VSS
						40	VSS
						40	VSS
						50	VSS
						50	VSS
						60	VSS
						60	VSS
						72	VSS
						72	VSS
						80	VSS
JP3		JP2				80	VSS
JP3		JP2					VSS
3	BS#	3	RD/WR#				S1D13705F00A
2	BS#	2	RD/WR#				S1D13705F00A
1	IOVDD	1	IOVDD
	IOVDD		IOVDD
HEADER 3		HEADER 3

			R1	R2	R3	R4	R5	R6	CNF[0..3]
			R1	R2	R3	R4	R5	R6
			15K	15K	15K	15K	15K	15K
		S1
		1	12					CNF0
		2	11					CNF1
		3	10					CNF2
		4	9					CNF3
		5	8					ADDR
		6	7					ADDR
		6	7					SUSPEND
								SUSPEND
		SW DIP-6
LCDPWR	43			LCDPWR
LCDPWR				LCDPWR
FPFRAME	39			FPFRAME
FPFRAME	38			FPFRAME
FPLINE	38			FPLINE
FPLINE	28			FPLINE
FPSHIFT	28			FPSHIFT
FPSHIFT	42			FPSHIFT
DRDY	42			DRDY
DRDY				DRDY
		FPDAT[0..7]		FPDAT[0..7]
				FPDAT[0..7]
FPDAT0	37	FPDAT0
FPDAT1	36	FPDAT1
FPDAT2	35	FPDAT2
FPDAT3	34	FPDAT3
FPDAT4	33	FPDAT4
FPDAT5	32	FPDAT5
FPDAT6	31	FPDAT6
FPDAT7	30	FPDAT7
FPDAT8/GPIO1	26			FPDAT8
FPDAT9GPIO2	25			FPDAT9
FPDAT9GPIO2	24			FPDAT9
FPDAT10/GPIO3	24			FPDAT10
FPDAT10/GPIO3	23			FPDAT10
FPDAT11/GPIO4	23			FPDAT11
FPDAT11/GPIO4				FPDAT11
		CNF[0..3]		CNF[0..3]
				CNF[0..3]
CNF0	49	CNF0
CNF0	48	CNF1
CNF1	48	CNF1
CNF1	47	CNF2
CNF2	47	CNF2
CNF2	46	CNF3
CNF3	46	CNF3
CNF3
GPIO0	22			SUSPEND
GPIO0				SUSPEND

Epson Research & Development, Inc.
S5U13705B00C ISA-Bus Rev0. 1Evaluation. Board : 13705F00A Chip
Size	Document Number				Rev
B					1.0
Date:	Monday, January 04, 1999	Sheet	1	of	4

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Schematic Diagrams

Epson Research and Vancouver

User Manual 01/02/13

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Design Center

Development

Image 308

Epson technical manual Schematic Diagrams, S1D13705B00C Schematic Diagram 1

Contents

S1D13705 Document No. X27A-Q-001-04 This page Left Blank Customer Support Information This page Left Blank S1D13705 Embedded Memory LCD Controller February Software Suspend mode LCD power-down sequencing Embedded 80K byte Sram display buffer Hardware Functional Specification Document Number X27A-A-001-10 This page Left Blank Table of Contents Power Save Modes RegistersSwivelView Mechanical Data List of Tables This page Left Blank List of Figures 2 Bit-per-pixel Monochrome Mode Data Output Path Overview Description IntroductionScope Features Integrated Frame BufferCPU Interface Display Support Display Modes Clock SourceMiscellaneous Package Typical System Implementation Diagrams Typical System Diagram SH-4 Bus Typical System Diagram M68K #1 Bus Typical System Diagram Generic #1 Bus Functional Block Diagram Functional Block DescriptionsHost Interface Memory Controller Power Save Power Save contains the power save mode circuitryLook-Up Table LCD Interface Package type 80 pin surface mount QFP14 PinsPinout Diagram Pin Description KeyPin Names Type Pin # Cell Description For SH-3/SH-4 mode, this pin inputs the write enable signal Input This pin inputs the chip select signalFor MC68K #1, this pin inputs the R/W# signal For the lower data byte WE0# Pin Name Type Pin # Cell Power Supply Clock InputMiscellaneous Pin Name Type Pin # Driver Description Summary of Configuration Options Summary of Power On/Reset OptionsHost Bus Interface Pin Mapping Host Bus Interface Pin Mapping Bit Pin Name Bit Dual Single 12-bit Format LCD Interface Pin MappingLCD Interface Pin Mapping C. Characteristics Input SpecificationsAbsolute Maximum Ratings Recommended Operating Conditions for Core VDD = 3.3V ± 10% Output Specifications Bus Interface Timing 1 SH-4 Interface Timing Symbol Parameter Min Max Units Bus Clock frequency MHzBus Clock period T11 Rising edge CSn# to RDY# high impedance 2 SH-3 Interface Timing T12 T13T14 T15 D150 Write T16 T17 D150 Symbol Parameter Min Maxa Units UDS#, LDS# falling edge to D150 valid write cycle Motorola MC68K #1 Interface TimingAS# high to DTACK# high AS# high to DTACK# high impedance Motorola MC68K #2 Interface Timing AS# high to DSACK1# high AS# high to DSACK1# high impedanceDS# falling edge to D3116 valid write cycle AS#, DS# rising edge to D3116 high impedance Generic #1 Interface Timing Generic #1 Timing Generic #2 Interface Timing Generic #2 Timing Clock Input Requirements Input Clock Frequency Clki MHzInput Clock period Clki Input Clock Pulse Width High Clki Input Clock Pulse Width High Bclk Input Clock Frequency Bclk MHzInput Clock period Bclk Power On/Reset Timing Symbol Parameter Min Typ Max UnitsDisplay Interface REG03h to FPLINE, FPFRAME, FPSHIFT, FPDAT, Drdy Power Down/Up Timing Lcdpwr Override REG03h bit HW Power SaveREG03h bits FP Signals Active Inactive Active Inactive Single Monochrome 4-Bit Panel Timing 11 Single Monochrome 4-Bit Panel Timing Sync Timing Data Timing Single Monochrome 8-Bit Panel Timing 13 Single Monochrome 8-Bit Panel Timing = REG08h bits 4-0 x 8 + 4Ts Single Color 4-Bit Panel Timing 15 Single Color 4-Bit Panel Timing = REG08h bits 4-0 x 8 + 1.5Ts Single Color 8-Bit Panel Timing Format 17 Single Color 8-Bit Panel Timing Format T6a T6b T7a T14 T11 19 Single Color 8-Bit Panel Timing Format = REG08h bits 4-0 x 8 + 1Ts Dual Monochrome 8-Bit Panel Timing 21 Dual Monochrome 8-Bit Panel Timing = REG04h bits 6-0+1 x 8 + REG08h bits 4-0 + 4 x 8 x 2Ts Dual Color 8-Bit Panel Timing 23 Dual Color 8-Bit Panel Timing = REG08h bits 4-0 x 2x 8 + 17Ts 10 9/12-Bit TFT/D-TFD Panel Timing 25 12-Bit TFT/D-TFD Panel Timing 26 TFT/D-TFD A.C. Timing 18 TFT/D-TFD A.C. Timing Registers Register MappingRegister Descriptions Bit Active high Panel Data FormatColor/Mono Dual/Single Data Width Bit Function Don’t care Gray Scale/Color Mode Selection Color/Mono Bit-Per-Pixel Bit Display ModeHigh Performance Selection High Performance BPP Bit Display Modes Video data is inverted after the Look-Up Table Video Mode Select Options belowInverse Video Mode Select Options Hardware Power Save/GPIO0 Operation Software Power Save Mode Selection Size Bit This register must not be set to a value less than 03hVertical Panel Following constraint must be satisfied Fpline Start Vertical Non MOD Rate Bit Screen 1 Start Screen 2 Start Vertical Size Bit MemoryOffset Bit Screen-Register Relationship, Split Screen LUT Address REG18h Gpio Configuration Control Register LUT Data Bit Selection of SwivelView Mode SwivelView Mode Enable Mode Select Selection of Pclk and Mclk in SwivelView Mode Create a virtual image in SwivelView modePixel Clock Pclk Select Mode Enable Mode Select Where CLK is Clki REG02h bit 4 = 0 or CLKI/2 REG02h bit 4 = TFT/D-TFD and Passive Single-Panel modes Passive Dual-Panel modeFrame Rate Calculation Display Data Formats 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Bit-per-pixel Monochrome mode Look-Up Table ArchitectureMonochrome Modes Green Look-Up Table LUT is used for all monochrome modes 4 Bit-per-pixel Monochrome Mode Data Output Path Bit-per-pixel Color Mode Color Modes 2 Bit-per-pixel Color Mode Data Output Path 4 Bit-per-pixel Color Mode Data Output Path 8 Bit-per-pixel Color Mode Data Output Path Default SwivelView Mode SwivelView Where bpb is bits-per-byte and bpp is bits-per-pixel How to Set Up Default SwivelView ModeWhere bpp is bits-per-pixel and bpb is bits-per-byte Alternate SwivelView Mode Start Address 480 Image refreshed by S1D13705 How to Set Up Alternate SwivelView Mode Comparison Between Default and Alternate SwivelView Modes SwivelView Mode LimitationsDefault and Alternate SwivelView Mode Comparison Default SwivelView Mode Alternate SwivelView Mode Hardware Power Save Mode Power Save ModesSoftware Power Save Mode Power Save Mode Function Summary Panel Power Up/Down SequencePower Save Mode Function Summary Hardware Software Normal Turning Off Bclk Between Accesses Software Power Save Clock Requirements S1D13705 Internal Clock Requirements Mechanical Data QFP14 80 pin Unit mm14.0 ± 12.0 ± Index 125 Sales and Technical Support Japan North America Taiwan This page Left Blank Programming Notes and Examples Document Number X27A-G-002-03 This page Left Blank LCD Power Sequencing and Power Save Modes Introduction InitializationMemory Models Look-Up Table LUT Identifying the S1D13705 Hardware Abstraction Layer HAL Sample Code S1D13705 Initialization Sequence This page Left Blank Introduction Register Values InitializationDisplay Buffer Location Register Value hex See Also Frame Rate CalculationS1D13705 Initialization Sequence Where Pclk = Pixel clock in Hz For a dual passive panel the formula is= Horizontal Display Period in pixels = Horizontal Non-Display Period in pixels Epson Research and Development Bit Pixel Memory Models1 Bit-Per-Pixel 2 Colors/Gray Shades Pixel Bit 2 Bit-Per-Pixel 4 Colors/Gray Shades4 Bit-Per-Pixel 16 Colors/Gray Shades Eight Bit-Per-Pixel 256 Colors Green bit Look-Up Table LUT Look-Up Table Registers LUT Data Look-Up Table Organization Color ModesIndex Red Green Blue Unused entries Example LUT Values for 2 Bpp Color Mode Indicates unused entries Bpp color Index Index Address Red Green Blue Gray Shade ModesRecommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade Suggested LUT Values for 4 Bpp Gray Shade Advanced Techniques Virtual Display Registers ExamplesREG11h Memory Address Offset Register Offset Panning and Scrolling Number of Pixels Panned Using Start Address REG0Ch Screen 1 Display Start Address 0 LSBREG0Dh Screen 1 Display Start Address 1 MSB REG10h Screen 1 Display Start Address 2 MSB Panning to the left To scroll down Split Screen 320x240 Single Panel For Split Screen REG12 Screen 1 Vertical Size LSB REG13 Screen 1 Vertical Size MSB REG0Eh Screen 2 Display Start Address 0 LSB REG0Fh Screen 2 Display Start Address 1 MSB Examples LCD Power Sequencing and Power Save Modes LCD Power SequencingREG03h Mode Register Hardware Software Power Save Override Enable Bit LCD Enable/Disable Introduction To Hardware Rotation Default Portrait ModeHardware Rotation Portrait Alternate Portrait Mode REG1Bh Portrait Mode Register REG0Ch Screen 1 Start Word Address LSBREG0Dh Screen 1 Start Word Address MSB REG0Eh Screen 1 Start Word Address MSB Epson Research and Development Default and Alternate Portrait Mode Comparison Default Portrait Mode Alternate Portrait ModePower of 2. In most cases, a virtual Limitations Examples Vancouver Design Center 16 , 000 FrameRate Vancouver Design Center Identifying the S1D13705 Introduction Contents of the HalstructHardware Abstraction Layer HAL Function Description Using the HAL libraryAPI for 13705HAL Register / Memory Access SeSetInit InitializationInt seRegisterDeviceconst Lphalstruc lpHalInfo General HAL Support Int seGetIdint * pId Int seGetBytesPerScanlineint * pBytes Int seSetBitsPerPixelint BitsPerPixelInt seGetBitsPerPixelint * pBitsPerPixel Int seGetLastUsableBytelong * plLastByte Int seDelayint MilliSecondsInt seGetScreenSizeint * Width, int * Height Advanced HAL Functions Int seSetHighPerformanceBOOL OnOffInt seSetPortraitMethod int Style Int seSetHWRotateint Rotate Int seSplitInitWORD Scrn1Addr, Word Scrn2Addr Int seSplitScreenint Screen, int VisibleScanlines SeVirtInit must be been called before calling seVirtMove Int seVirtInitDWORD VirtX, Dword * VirtYInt seVirtMoveint Screen, int x, int y Register / Memory Access Int seGetRegint Index, Byte * pValueInt seSetRegint Index, Byte Value Int seReadDisplayByteDWORD Offset, Byte *pByte Int seReadDisplayDwordDWORD Offset, Dword *pDword Int seWriteDisplayBytesDWORD Offset, Byte Value, Dword Count Int seSetPowerSaveModeint PwrSaveMode Drawing Int seSetPixellong x, long y, Dword ColorInt seGetPixellong x, long y, Dword *pColor Int seDrawLineint x1, int y1, int x2, int y2, Dword Color Int seGetLutBYTE *pLUT, int Count LUT ManipulationInt seSetLutBYTE *pLut, int Count Int seSetLutEntryint Index, Byte *pEntry Int seGetLutEntryint index, Byte *pEntry Porting Libse to a new target platform Building the Libse library for SH3 target example Building the HAL library for the target example Sample code using the S1D13705 HAL API Sample Code Epson Research and Development Sample code without using the S1D13705 HAL API Purple Pbyte Vancouver Design Center Pclk Vancouver Design Center Epson Research and Development Vancouver Design Center NULL, OPENEXISTING,FILEATTRIBUTENORMAL, Null Vancouver Design Center Header Files Bool Sizeversion Errfailed Function PROTO-TYPES HAL EXE Vancouver Design Center Epson Research and Development This page Left Blank X27A-R-001-03 S1D13705 Register Summary X27A-R-001-03 01/02/13 13705CFG Configuration Program Document Number X27A-B-001-03 This page Left Blank 13705CFG This page Left Blank 13705CFG S1D13705 Supported Evaluation Platforms Installation Usage 13705CFG Configuration Tabs General Tab Decode Addresses Values for the Register address and DisplayAtion platform are examples of possible implementa If your hardware implementation differs from Display which requires more memory but uses less PowerPreferences Tab For details see the S1D13705 Hardware Functional Specification, document number X27A-A-001-xxClocks Tab Actual Clki frequency used for configuration is Source for both Pclk and MclkClki frequency must be selected from the drop Down list or by entering the desired frequency in MHz Panel Tab Ically for configuring 8-bit color STN panels 8 bit. When an active panel type is selectedWhen the panel type is TFT, Single is automatically These settings define the polarity of the Fpline Refer to S1D13705 Hardware Functional Specifi Complete description of the Fpframe pulse settings Panel manufacturers recommended settings. If the fileSettings contained in the file Cation, document number X27A-A-001-xx, for a Hardware Power Save function is not available Panel Power TabGPIO0 is enabled. When this box is unchecked, Registers Tab 13705CFG Menus Open Save Save As Configure Multiple Export Enable Tooltips CommentsERD on the Web About 13705CFG 13705SHOW Demonstration Program Document No. X27A-B-002-02 This page Left Blank 13705SHOW Download the program 13705SHOW to the system Use alternate portrait modeContinuously update display memory PC platform at the prompt, type Error Did not find a 13705 device Program Messages This page Left Blank 13705SPLT Display Utility Document No. X27A-B-003-02 This page Left Blank 13705SPLT Enables manual split screen operation Enables automatic split screen operationTimer is used to move screen Manual mode Move Screen 2 up Move Screen 2 down 13705SPLT Example This page Left Blank 13705VIRT Display Utility Document No. X27A-B-004-02 This page Left Blank 13705VIRT Defaults to virtual width = = physical width x Force landscape display mode to be setForce portrait display mode to be set Enable alternate portrait mode. Selecting this 13705VIRT Example Virtual screen shows in the upper rightDisplay Virtual screen shows in the lower left Unable to use virtual mode at xx BPP 13705PLAY Diagnostic Utility Document No. X27A-B-005-04 This page Left Blank 13705PLAY Writes data to the LUT index when data is Download the program 13705PLAY to the systemReads/writes the registers Writes data to the register specified by the index 13705PLAY Example Scripting Program Messages This page Left Blank 13705BMP Demonstration Program Document No. X27A-B-006-03 This page Left Blank 13705BMP currently views only Windows BMP format images 13705BMPAt the prompt, type This error message should never bee seen. Contact ERD Error Did not find an S1D13705 device 13705PWR Power Save Utility Document No. X27A-B-007-03 This page Left Blank 13705PWR Displays this usage message Sets enables hardware power save mode REG03h bitDownload the program 13705PWR to the system Error Did not find a 13705 device This page Left Blank Windows CE 2.x Display Drivers Document Number X27A-E-001-03 X27A-E-001-03 Windows CE 2.x Display Drivers Example Driver Builds Ddi.dll $FLATRELEASEDIR\ddivga2.dll NK SH Ddi.dll $FLATRELEASEDIR\ddivga8.dll NK SHDdi.dll $FLATRELEASEDIR\ddis364.dll With this line Ddi.dll $FLATRELEASEDIR\EPSON.dll Vancouver Design Center Find the section shown below, and insert the lines as marked If CEPCDDIS1D13705 Ddi.dll $FLATRELEASEDIR\ddis364.dll NK SH Endif Epson Research and Development Installation for Cepc Environment Copy NK.BIN and HIMEM.SYS to c\ Boot the system Configuration Compile Switches Mode File Comments This page Left Blank Wind River WindML v2.0 Display Drivers Document Number X27A-E-002-03 X27A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers If necessary, generate a new mode0.h configuration file Building a WindML v2.0 Display Driver Make CPU=PENTIUM ugl This page Left Blank Wind River UGL v1.2 Display Drivers Document Number X27A-E-003-02 X27A-E-003-02 Issue Date 01/02/13 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Linux Console Driver Document Number X27A-E-004-02 X27A-E-004-02 Issue Date 01/09/19 Linux Console Driver Building the Console Driver for Linux Kernel Epson Research and Development Vancouver Design Center To the directory /usr/src/linux/drivers/video/epson Vancouver Design Center Epson Research and Development This page Left Blank QNX Photon v2.0 Display Driver Document Number X27A-E-005-01 This page Left Blank QNX Photon v2.0 Display Driver Configure the Driver Building the Photon v2.0 Display DriverUnpack the Graphics Driver Development Kit Archive Build the Driver Installing the Driver Run the Driver Comments S1D13XXX 32-Bit Windows Device Driver Installation Guide Document No. X00A-E-003-04 X00A-E-003-04 Issue Date 01/04/17 S1D13XXX 32-Bit Windows Device Driver Installation Guide Driver RequirementsWindows NT Version Video Controller S1D13xxx Display Type All ISA Bus Evaluation Cards WindowsAll PCI Bus Evaluation Cards Windows 98/ME Windows 95 OSR2 ADD/NEW Hardware Previous Versions of Windows All ISA Bus Evaluation Cards S5U13705B00C Rev .0 ISA Bus Document Number X27A-G-005-03 S1D13705 X27A-G-005-03 Issue Date 01/02/13 Installation and Configuration Parts List Schematic Diagrams This page Left Blank S1D13705B00C Schematic Diagram 1 of 4 This page Left Blank Features Host Bus Selection Installation and ConfigurationConfiguration DIP Switch Settings Jumper Settings RD/WR# Signal Selection Pulled up to Iovdd No ConnectionBS# Signal Selection Pulled up to Iovdd No Connection Iovdd Selection LCD Signal Connector J5 Pinout PinsLCD Interface Pin Mapping Even CPU/Bus Interface Connector Pinouts CPU/BUS Connector H1 PinoutConnector Comments CPU/BUS Connector H2 Pinout Host Bus Interface Pin Mapping DB150 D150 WE1# Technical Description Embedded Memory Support ISA Bus Support Non-ISA Bus SupportDisplay Adapter Card Support Expanded Memory Manager Support Decoding Logic Clock Input Support LCD Panel Voltage Setting Power Save ModesMonochrome LCD Panel Support Color Passive LCD Panel Support 13 CPU/Bus Interface Header Strips Adjustable LCD Panel Negative Power SupplyAdjustable LCD Panel Positive Power Supply Parts List Item # Qty/board Designation Part Value Description Schematic Diagrams S1D13705B00C Schematic Diagram 1 S1D13705B00C Vancouver Epson Research S1D13705B00C Schematic Diagram 4 This page Left Blank Document Number X27A-G-014-02 S1D13705 X27A-G-014-02 Issue Date 2002/09/16 Introduction Features Installation and Configuration Parts List Schematics Board Layout Technical SupportCPU Interface LCD Interface Pin Mapping Technical Description This page Left Blank Configuration DIP Switch SW1 Location This page Left Blank Introduction Features Configuration DIP Switches Configuration DIP Switch SW1 Location SH-4 SH-3Big Endian bus interface Little Endian bus interface SW1-5 Not Used SW1-6 Configuration Jumpers Jumper SummaryJumper Function Position No Jumper PCI Bridge Fpga Configuration Jumper JP2 Location Configuration Jumper JP4 Location Configuration Jumper JP6 Location CPU Interface Pin Mapping CPU InterfaceCPU Interface Pin Mapping Connector Comments Pin No CPU Bus Connector Pin MappingCPU Bus Connector H1 Pinout CPU Bus Connector H2 Pinout Dual LCD Signal Connector J52LCDPWR on J5 can be inverted by setting JP6 to Adjustable LCD Panel Positive Power Supply Vddh PCI Bus SupportDirect Host Bus Interface Support S1D13705 Embedded Memory Adjustable LCD Panel Negative Power Supply Vlcd Passive/Active LCD Panel Support Clock Options Software Document Sources ReferencesDocuments Quantity Reference Part Description RD-0412 Xentek RD-0412, positive power Supply EPN001 Xentek EPN001, negative power SupplyEPF6016TC144-2 Altera EPF6016TC144-2 Pin DIP socket Machined socket, 8-pin Schematics S1D13705B00C Schematics 1 Schematics 2 S1D13705B00C S1D13705B00C Schematics 3 S1D13705B00C Schematics 4 S1D13705B00C Schematics 5 Board Layout Technical Support Epson LCD Controllers S1D13705 Windows CE 3.x Display Drivers Document Number X27A-E-006-01 X27A-E-006-01 Windows CE 3.x Display Drivers Example Driver Builds If CEPCDDIS1D13X0X Ddi.dll $FLATRELEASEDIR\ddiflat.dll NK SH If Cepcddiflat If CEPCDDIS1D13X0X Endif Epson Research and Development Installation for Cepc Environment EnablePreferVmem GrayPalette Resource Management Issues Vancouver Design Center Simple Display Driver Configuration Comments Interfacing to the Toshiba Mips TMPR3912 Microprocessor Document Number X27A-G-004-02 This page Left Blank Software Technical Support Using the ITE IT8368E PC Card BufferDirect Connection to the Toshiba TMPR3912 This page Left Blank S1D13705 to TMPR3912 Connection Using an IT8368E S1D13705 to TMPR3912 Direct Connection This page Left Blank Introduction Interfacing to the TMPR3912 S1D13705 Host Bus Interface Host Bus Pin ConnectionS1D13705 Generic #1 Generic #2 Pin Names AB151 A151 Generic #1 Interface Mode Generic #2 Interface Mode Direct Connection to the Toshiba TMPR3912 General Description S1D13705 Configuration S1D13705 Configuration for Direct ConnectionMemory Mapping and Aliasing Big Endian Using the ITE IT8368E PC Card Buffer Hardware Description S1D13705 to TMPR3912 Connection Using an IT8368E IT8368E Configuration 16M byte Card 1 IO16M byte At 128K byte intervals S1D13705 Configuration Using the IT8368E = configuration for connection using ITE IT8368E16M byte Card 2 IO 32M byte Card 2 Attribute Software Toshiba Mips TMPR3912 Processor ITE IT8368E Japan North America Taiwan, R.O.CEurope Hong Kong Singapore Integrated Technology Express, Inc This page Left Blank S1D13705 Power Consumption Document Number X27A-G-006-02 S1D13705 Power Consumption X27A-G-006-02 S1D13705 Power Consumption S1D13705 Total Power Consumption Conditions Summary This page Left Blank Document Number X27A-G-007-04 X27A-G-007-04 Issue Date 01/02/13 Interfacing to the MC68VZ328 Introduction Interfacing to the MC68328Interfacing to the MC68EZ328 Technical Support List of Tables This page Left Blank Introduction Chip-Select Module Interfacing to the MC68328MC68328 System Bus S1D13705 Host Bus Interface Host Bus Pin ConnectionS1D13705 MC68K #1 Generic #1 Pin Names WE0# Connect to IO V DD Generic #1 Interface Mode 3 MC68K #1 Interface Mode Hardware Description Using The MC68K #1 Host Bus InterfaceMC68328 To S1D13705 Interface Using The Generic #1 Host Bus Interface 2 S1D13705 Hardware Configuration 3 MC68328 Chip Select ConfigurationSummary of Power-On/Reset Options Host Bus Interface Selection Epson Research and Development Interfacing to the MC68EZ328 MC68EZ328 System Bus S1D13705 Generic #1 Pin Names Generic #1 Interface Mode MC683EZ28 To S1D13705 Interface 3 MC68EZ328 Chip Select Configuration = configuration for MC68EZ328 support Epson Research and Development Interfacing to the MC68VZ328 MC68VZ328 System Bus S1D13705 Host Bus Interface Generic #1 Interface Mode 3 MC68K #1 Interface Mode MC68VZ328 To S1D13705 Interface CSB1 CS# = configuration for MC68VZ328 support 3 MC68VZ328 Chip Select and Pin Configuration Software Motorola Inc. Motorola Literature Distribution Center, 800 Motorola Dragonball Processors Interfacing to the NEC VR4102/VR4111 Microprocessor Document Number X27A-G-008-02 X27A-G-008-02 Issue Date 01/02/13 Host Bus Pin Connection Generic #2 Interface Mode Introduction Interfacing to the NEC VR4102/VR4111VR4102/VR4111 to S1D13705 Interface Epson LCD Controllers S1D13705 NEC Electronics Inc This page Left Blank NEC VR4102/VR4111 Read/Write Cycles This page Left Blank Introduction Overview Interfacing to the NEC VR4102/VR4111NEC VR4102/VR4111 System Bus LCD Memory Access Cycles Lcdrdy S1D13705 Generic #2 Pin Names Generic #2 Interface Mode VR4102/VR4111 to S1D13705 Interface Busclk BS# RD/WR# S1D13705 Hardware Configuration See Host Bus Selection table below NEC VR4102/VR4111 Configuration Software References Santa Clara California Tel 800 Fax 800 NEC Electronics IncNEC Electronics Inc. U.S.A This page Left Blank Interfacing to the PC Card Bus Document Number X27A-G-009-02 This page Left Blank Memory Access Cycles Interfacing to the PC Card BusS1D13705 Bus Interface PC Card to S1D13705 Interface This page Left Blank PC Card Read Cycle This page Left Blank Introduction Memory Access Cycles Interfacing to the PC Card BusPC Card System Bus PC Card Overview PC Card Read Cycle S1D13705 Bus Interface Generic #2 Interface Mode PC Card to S1D13705 Interface Hardware Connections Signal Low High Register/Memory Mapping Software PC Card Pcmcia Standard March PC Card Standard Pcmcia Interfacing to the Motorola MPC821 Microprocessor Document Number X27A-G-010-02 X27A-G-010-02 Issue Date 01/02/13 MPC821 to S1D13705 Interface Host Bus Interface Modes Generic #1 Host Bus Interface ModeIntroduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction MPC821 Bus Overview Interfacing to the MPC821MPC8xx System Bus Power PC Memory Read Cycle Normal Non-Burst Bus Transactions Power PC Memory Write Cycle Burst Cycles Memory Controller Module General-Purpose Chip Select Module Gpcm User-Programmable Machine UPM Host Bus Interface Modes Generic #1 Host Bus Interface Mode MPC821 to S1D13705 Interface Typical Implementation of MPC821 to S1D13705 Interface MPC821ADS Evaluation Board Hardware Connections List of Connections from MPC821ADS to S1D13705 P6-A14 WE0# P12-A1, P12-B1, P12-A2, P12-B2P12-A3, P12-B3, P12-A4, P12-B4 P12-A5, P12-B5, P12-A6, P12-B6 Configuration Settings MPC821 Chip Select Configuration Test Software 1FFE0 Epson Research and Development Software Motorola Inc. Literature Distribution Center 800 Epson LCD/CRT Controllers S1D13705 Motorola MPC821 Processor Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X27A-G-011-02 X27A-G-011-02 Issue Date 01/02/13 Epson LCD Controllers S1D13705 Motorola MCF5307 Processor Host Bus Pin Connection Generic #1 Interface ModeIntroduction Interfacing to the MCF5307 This page Left Blank List of Tables This page Left Blank Introduction Interfacing to the MCF5307 MCF5307 System Bus MCF5307 Memory Read Cycle Chip-Select Module S1D13705 Bus Interface Generic #1 Interface Mode MCF5307 To S1D13705 Interface Typical Implementation of MCF5307 to S1D13705 Interface Little Endian Big Endian = configuration for MFC5307 support MCF5307 Chip Select Configuration Software References Motorola MCF5307 Processor Interfacing to the Philips Mips PR31500/PR31700 Processor Document Number X27A-G-012-02 This page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 to PR31500/PR31700 Direct Connection This page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13705 Host Bus Interface Generic #1 Interface Mode Generic #2 Interface Mode Direct Connection to the Philips PR31500/PR31700 S1D13705 to PR31500/PR31700 Direct Connection Memory Mapping and Aliasing S1D13705 Configuration and Pin Mapping Using the ITE IT8368E PC Card Buffer S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 S1D13705 aliased 128 times 0900 0000h S1D13705 Configuration Software Philips Mips PR31500/PR31700 Processor Philips Semiconductors S5U13704/5 TMPR3912/22U CPU Module Document Number X00A-G-004-02 S5U13704/5 TMPR3912/22U CPU Module Table of Contents This page Left Blank List of Tables List of Figures This page Left Blank General Description S1D13704/5 Bus Interface Bus Interface Modes Generic #2 Interface Mode TMPR3912/22U and S1D13704/5 Interface Hardware Connections S1D13704/5 Configuration and Pin Mapping = configuration for Toshiba TMPR3912/22U host bus interfaceMemory Mapping and Aliasing S1D13704/5 Generic #2 Interface Pin Mapping Clock Signals Busclk LCD Connectors 1 50-pin LCD Module Connector, J3CPU Module Description Clki Standard Epson LCD Connector, J4 LCD Controller 1 S1D13704 vs. S1D13705Lcdpwr Polarity 3 S1D13704\75 Chip Select This page Left Blank Interfacing to the NEC VR4181A Microprocessor Document Number X27A-G-013-02 X27A-G-013-02 VR4181A to S1D13705 Interface NEC VR4181A System Bus Overview LCD Memory Access SignalsIntroduction Interfacing to the NEC VR4181A This page Left Blank Typical Implementation of VR4181A to S1D13705 Interface This page Left Blank Introduction Interfacing to the NEC VR4181A NEC VR4181A System Bus LCD Memory Access Signals BHE# Generic #2 Interface Mode VR4181A to S1D13705 Interface Typical Implementation of VR4181A to S1D13705 Interface S1D13705 Hardware Configuration NEC VR4181A Configuration Software References Technical Support This page Left Blank Interfacing to an 8-bit Processor Document Number X27A-G-015-01 X27A-G-015-01 Issue Date 01/12/20 Interfacing to an 8-bit Processor Generic 8-bit Processor System BusBit Processor to S1D13705 Interface Epson LCD/CRT Controllers S1D13705 This page Left Blank List of Tables This page Left Blank Introduction Interfacing to an 8-bit Processor Generic 8-bit Processor System Bus S1D13705 Generic #2 Description Pin Names Generic #2 Interface Mode Bit Processor to S1D13705 Interface = required configuration for this application Little Endian Big Endian Software References Technical Support This page Left Blank