Epson S1D13705 technical manual LCD Enable/Disable

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	Vancouver Design Center

6.3 LCD Enable/Disable

The descriptions below cover manually powering the LCD panel up and down. Use the sequences described in this section if the power supply connected to the panel requires more than 127 frames to discharge on power-down, or if the panel requires starting the LCD logic well in advance of enabling LCD power. Currently there are no known circumstances where the LCD logic must be active well in advance of LCD power.

Note

If 127 frame period is to long, blank the display, then reprogram the Horizontal and Ver- tical sizes to produce a shorter frame period before using these methods.

Power On/Enable Sequence

The following is a sequence for manually powering-up an LCD panel if LCD power had to be applied later than LCD logic.

1.Set REG[03h] bit 3 (LCDPWR Override) to “1”. This ensures that LCD power will be held disabled.

2.Enable LCD logic. This is done by either setting the GPIO0 pin low to disable hard- ware power save mode and/or by setting REG[03h] bits 1-0 to “11” to disable soft- ware power save.

3.Count “x” Vertical Non-Display Periods (OPTIONAL).

“x” corresponds the length of time LCD logic must be enabled before LCD power-up, converted to the equivalent vertical non-display periods. For example, at 72 HZ count- ing 36 non-display periods results in a one half second delay.

4.Set REG[03h] bit 3 to “0” to enable LCD Power.

Power Off/Disable Sequence

The following is a sequence for manually powering-down an LCD panel. These steps would be used if the power supply discharge requirements are larger than the default 127 frames.

1.Set REG[03h] bit 3 (LCDPWR Override) to “1” which will disable LCD Power.

2.Count “x” Vertical Non-Display Periods.

“x” corresponds to the power supply discharge time converted to the equivalent verti- cal non-display periods. (see the previous example)

3.Disable the LCD logic by setting the software power save in REG[03h] or setting hardware power save via GPIO0. Keep in mind that after setting the power save mode there will be 127 frames before the LCD logic signals are disabled.

S1D13705	Programming Notes and Examples
X27A-G-002-03	Issue Date: 02/01/22