Epson Research and Development

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4 Functional Block Diagram

 

 

40k x 16-bit SRAM

 

 

 

 

Memory

Power Save

 

 

Register

Controller

 

 

 

 

 

Clocks

 

 

 

 

LCD

LCD

 

 

 

 

Generic MPU

 

 

 

 

MC68K

Host

 

I/F

 

SH-3

I/F

 

Look-Up

 

SH-4

 

 

 

 

 

 

 

 

Table

 

 

 

 

Sequence Controller

 

 

Bus Clock

Memory Clock

Pixel Clock

 

Figure 4-1: System Block Diagram Showing Data Paths

4.1 Functional Block Descriptions

4.1.1 Host Interface

The Host Interface provides the means for the CPU/MPU to communicate with the display buffer and internal registers.

4.1.2 Memory Controller

The Memory Controller arbitrates between CPU accesses and display refresh accesses. It also generates the necessary signals to control the SRAM frame buffer.

4.1.3 Sequence Controller

The Sequence Controller controls data flow from the Memory Controller through the Look- Up Table and to the LCD Interface. It also generates memory addresses for display refresh accesses.

Hardware Functional Specification

S1D13705

Issue Date: 02/02/01

X27A-A-001-10

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Epson S1D13705 technical manual Functional Block Diagram, Functional Block Descriptions, Host Interface, Memory Controller