Epson S1D13705 - page 539

Epson Research and Development Page 11

Vancouver Design Center

Interfacing to the NEC VR4181A™ Microprocessor S1D13705

Issue Date: 01/02/13 X27A-G-013-02

3.2 Generic #2 Interface Mode

Generic #2 interface mode is a general and non-processor-specific interface mode on the

S1D13705. The Generic # 2 interface mode was chosen for this interface due to the

simplicity of its timing and compatibil it y with the VR4181A control signals.

The interface requires the following signals :

• BUSCLK is a clock input which synchronizes transfers between the host CPU and the

S1D13705. It is separate from the input clock (CLKI) and is typically driven by t he host

CPU system clock.

• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect

directly to the CPU address and data bus, respectively. On 32-bit big endian architec-

tures such as the Power PC, the data bus would connect to the high-order data lines; on

little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data

lines. The hardware engineer must ensure that CNF3 selects the proper endian mode

upon reset.

• Chip Select (CS#) is driven by decoding the high-order address lines to select th e proper

register and memory address space.

• WE1# is the high byte enable for both read and write cycles.

• WE0# is the write enable signal for the S1D13705, to be driven low when th e host CPU

is writing data from the S1D13705.

• RD# is the read enable for the S1D13705, to be driven low when the host CPU is

reading data from the S1D13705.

• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates

when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host

CPU accesses to the S1D13705 may occur asynchronously to the display update, it is

possible that contention may occur in accessing the S1D13705 internal registers or

memory. The WAIT# line resolves these contentions by forcing the host to wait until the

resource arbitration is complete. This signal is active low and may need to be invert ed if

the host CPU wait state signal is active hi gh.

• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-

face for Generic #2 mode. However, BS# is used to configure the S1D13705 for

Generic #2 mode and should be tied high (connected to IOVDD). RD/WR# should also

be tied high.

Contents

Main Page Customer Support Information Comprehensive Support Tools Evaluation / Demonstration Board Chip Documentation Software Page GRAPHICS S1D13705 S1D13705 Embedded Memory LCD Controller X27A-C-001-04 2 GRAPHICS S1D13705 Memory Interface CPU Interface Display Support Clock Source Page Page Page Page Page Page Page Page 1.1 Scope 1.2 Overview Description 2 Features 2.1 Integrated Frame Buffer 2.2 CPU Interface 2.3 Display Support 2.4 Display Modes 2.5 Clock Source 2.6 Miscellaneous 2.7 Package Page 12 Epson Research and Development 3 Typical System Implementation Diagrams Figure 3-1: Typical System Diagram (SH-4 Bus) Figure 3-2: Typical System Diagram (SH-3 Bus) 8-bit SH-4 Figure 3-3: Typical System Diagram (M68K #1 Bus) Figure 3-4: Typical System Diagram (M68K #2 Bus) 4-bit MC68000 8-bit Figure 3-5: Typical System Diagram (Generic #1 Bus) Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus) 12-bit TFT GENERIC #1 9-bit TFT 4 Functional Block Diagram 4.1 Functional Block Descriptions 4.1.1 Host Interface 4.1.2 Memory Controller 4.1.3 Sequence Controller Page 5 Pins 5.1 Pinout Diagram Figure 5-1: Pinout Diagram Package type: 80 pin surface mount QFP14 S1D13705 5.2 Pin Description Key: 5.2.1 Host Interface Page 5.2.2 LCD Interface 5.2.3 Clock Input 5.2.4 Miscellaneous 5.2.5 Power Supply 5.3 Summary of Configuration Options 5.4 Host Bus Interface Pin Mapping Table 5-1: Summary of Power On/Reset Options Table 5-2: Host Bus Interface Pin Mapping 5.5 LCD Interface Pin Mapping Table 5-3: LCD Interface Pin Mapping 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Table 6-2: Recommended Operating Conditions for Core VDD = 3.3V 10% Table 6-3: Input Specifications Table 6-4: Output Specifications 7 A.C. Characteristics 7.1 Bus Interface Timing 7.1.1 SH-4 Interface Timing Figure 7-1: SH-4 Timing CKIO may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-1: SH-4 Timing 7.1.2 SH-3 Interface Timing Figure 7-2: SH-3 Bus Timing CKIO may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-2: SH-3 Bus Timing 7.1.3 Motorola MC68K #1 Interface Timing Figure 7-3: MC68K #1 Bus Timing (MC68000) CLK may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-3: MC68K #1 Bus Timing (MC68000) 7.1.4 Motorola MC68K #2 Interface Timing Figure 7-4: MC68K #2 Timing (MC68030) CLK may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-4: MC68K #2 Timing (MC68030) 7.1.5 Generic #1 Interface Timing Figure 7-5: Generic #1 Timing BCLK may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-5: Generic #1 Timing 7.1.6 Generic #2 Interface Timing Figure 7-6: Generic #2 Timing BCLK may be turned off (held low) between accesses - see Section 13.5, Turning Off Table 7-6: Generic #2 Timing 7.2 Clock Input Requirements Figure 7-7: Clock Input Requirements for CLKI When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1. Table 7-7: Clock Input Requirements for CLKI Figure 7-8: Clock Input Requirements for BCLK Table 7-8: Clock Input Requirements for BCLK 7.3 Display Interface 7.3.1 Power On/Reset Timing Figure 7-9: LCD Panel Power On/Reset Timing Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock. Table 7-9: LCD Panel Power On/Reset Timing 7.3.2 Power Down/Up Timing Figure 7-10: Power Down/Up Timing Table 7-10: Power Down/Up Timing 7.3.3 Single Monochrome 4-Bit Panel Timing Figure 7-11: Single Monochrome 4-Bit Panel Timing Figure 7-12: Single Monochrome 4-Bit Panel A.C. Timing 4. t6min = [(REG[08h] bits 4-0) x 8 + 2]Ts 5. t7min = [(REG[08h] bits 4-0) x 8 + 11]Ts Table 7-11: Single Monochrome 4-Bit Panel A.C. Timing 7.3.4 Single Monochrome 8-Bit Panel Timing Figure 7-13: Single Monochrome 8-Bit Panel Timing Figure 7-14: Single Monochrome 8-Bit Panel A.C. Timing 4. t6min = [(REG[08h] bits 4-0) x 8 + 4]Ts 5. t7min =[(REG[08h] bits 4-0) x 8 + 13]Ts Table 7-12: Single Monochrome 8-Bit Panel A.C. Timing 7.3.5 Single Color 4-Bit Panel Timing Figure 7-15: Single Color 4-Bit Panel Timing Figure 7-16: Single Color 4-Bit Panel A.C. Timing 4. t6min = [(REG[08h] bits 4-0) x 8 + 1.5]Ts 5. t7min = [(REG[08h] bits 4-0) x 8 + 10]Ts Table 7-13: Single Color 4-Bit Panel A.C. Timing 7.3.6 Single Color 8-Bit Panel Timing (Format 1) Figure 7-17: Single Color 8-Bit Panel Timing (Format 1) Figure 7-18: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 7-14: Single Color 8-Bit Panel A.C. Timing (Format 1) 7.3.7 Single Color 8-Bit Panel Timing (Format 2) Figure 7-19: Single Color 8-Bit Panel Timing (Format 2) Figure 7-20: Single Color 8-Bit Panel A.C. Timing (Format 2) 4. t6min = [(REG[08h] bits 4-0) x 8 + 1]Ts 5. t7min = [(REG[08h] bits 4-0) x 8 + 10]Ts Table 7-15: Single Color 8-Bit Panel A.C. Timing (Format 2) 7.3.8 Dual Monochrome 8-Bit Panel Timing Figure 7-21: Dual Monochrome 8-Bit Panel Timing Figure 7-22: Dual Monochrome 8-Bit Panel A.C. Timing Table 7-16: Dual Monochrome 8-Bit Panel A.C. Timing 7.3.9 Dual Color 8-Bit Panel Timing Figure 7-23: Dual Color 8-Bit Panel Timing Figure 7-24: Dual Color 8-Bit Panel A.C. Timing Table 7-17: Dual Color 8-Bit Panel A.C. Timing 7.3.10 9/12-Bit TFT/D-TFD Panel Timing Figure 7-25: 12-Bit TFT/D-TFD Panel Timing Figure 7-26: TFT/D-TFD A.C. Timing Note: DRDY is used to indicate the first pixel Table 7-18: TFT/D-TFD A.C. Timing 8 Registers 8.1 Register Mapping 8.2 Register Descriptions Page Page Page Page This register must not be set to a value less than 03h. . REG[04h] Horizontal Panel Size Register Address = 1FFE4h Read/Write REG[05h] Vertical Panel Size Register (LSB) Address = 1FFE5h Read/Write REG[06h] Vertical Panel Size Register (MSB) Address = 1FFE6h Read/Write Page Page For SwivelView mode the most significant bit (bit 16) is located in REG[10h]. REG[0Ch] Screen 1 Start Address Register (LSB) Address = 1FFECh Read/Write REG[0Dh] Screen 1 Start Address Register (MSB) Address = 1FFEDh Read/Write REG[0Eh] Screen 2 Start Address Register (LSB) Address = 1FFEEh Read/Write Page Page Page Page Page 9 Frame Rate Calculation The following formulae are used to calcu la te the display frame rate. TFT/D-TFD and Passive Single-Panel modes Passive Dual-Panel mode Page 70 Epson Research and Development 10 Display Data Formats Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization 11 Look-Up Table Architecture The following figures are intended to show the display data output path only. When Video Data Invert is enabled the video data is inverted after the Look-Up Table. 11.1 Monochrome Modes The green Look-Up Table (LUT) is used for all monochrome modes. 1 Bit-per-pixel Monochrome mode 4 Bit-per-pixel Monochrome Mode Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path 11.2 Color Modes 1 Bit-per-pixel Color Mode Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path 2 Bit-per-pixel Color Mode Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path 4 Bit-per-pixel Color Mode Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path 8 Bit-per-pixel Color Mode Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path 12 SwivelView 12.1 Default SwivelView Mode 12.1.1 How to Set Up Default SwivelView Mode 12.2 Alternate SwivelView Mode 12.2.1 How to Set Up Alternate SwivelView Mode 12.3 Comparison Between Default and Alternate SwivelView Modes 12.4 SwivelView Mode Limitations Table 12-1: Default and Alternate SwivelView Mode Comparison 13 Power Save Modes 13.1 Software Power Save Mode 13.2 Hardware Power Save Mode 13.3 Power Save Mode Function Summary 13.4 Panel Power Up/Down Sequence 13.5 Turning Off BCLK Between Accesses 13.6 Clock Requirements 14 Mechanical Data Figure 14-1: Mechanical Drawing QFP14 15 Sales and Technical Support Page Page Page Page Page Page Page Page 2 Initialization 2.1 Display Buffer Location 2.2 Register Values 2.3 Frame Rate Calculation Page Page 3 Memory Models 3.1 1 Bit-Per-Pixel (2 Colors/Gray Shades) 3.2 2 Bit-Per-Pixel (4 Colors/Gray Shades) 3.3 4 Bit-Per-Pixel (16 Colors/Gray Shades) 3.4 Eight Bit-Per-Pixel (256 Colors) 4 Look-Up Table (LUT) 4.1 Look-Up Table Registers 4.2 Look-Up Table Organization 4.2.1 Color Modes Page Page Page Table 4-4: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) 4.2.2 Gray Shade Modes The following table shows the example values for 2 bit-per-pixel display mode. Table 4-6: Suggested Values for 2 Bpp Gray Shade Page 5 Advanced Techniques 5.1 Virtual Display 5.1.1 Registers 5.1.2 Examples 5.2 Panning and Scrolling 5.2.1 Registers 5.2.2 Examples Page 5.3 Split Screen 5.3.1 Registers Page 5.3.2 Examples 6 LCD Power Sequencing and Power Save Modes 6.1 LCD Power Sequencing 6.2 Registers 6.3 LCD Enable/Disable 7 Hardware Rotation 7.1 Introduction To Hardware Rotation 7.2 Default Portrait Mode Page 7.3 Alternate Portrait Mode 7.4 Registers Page 7.5 Limitations 7.6 Examples Page Page Page 8 Identifying the S1D13705 9 Hardware Abstraction Layer (HAL) 9.1 Introduction 9.2 Contents of the HAL_STRUCT 9.3 Using the HAL library 9.4 API for 13705HAL Table 9-1: HAL Functions (Continued) 9.4.1 Initialization 9.4.2 General HAL Support void seGetHalVersion(const char ** pVersion, const char ** pStatus, const char **pStatusRevision) int seSetBitsPerPixel(int BitsPerPixel) int seGetBitsPerPixel(int * pBitsPerPixel) int seGetBytesPerScanline(int * pBytes) int seGetScreenSize(int * Width, int * Height) int seDelay(int MilliSeconds) int seGetLastUsableByte(long * plLastByte) int seSetHighPerformance(BOOL OnOff) 9.4.3 Advanced HAL Functions int seSetHWRotate(int Rotate) Page int seVirtInit(DWORD VirtX, DWORD * VirtY) seVirtInit() must be been called before calli ng seVirtMove(). 9.4.4 Register / Memory Access Page 9.4.5 Power Save 9.4.6 Drawing Functionality differs from the 135x HAL. int seGetPixel(long x, long y, DWORD *pColor) int seDrawLine(int x1, int y1, int x2, int y2, DWORD Color) int seDrawRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) 9.4.7 LUT Manipulation int seGetLut(BYTE *pLUT, int Count) int seSetLutEntry(int Index, BYTE *pEntry) int seGetLutEntry(int index, BYTE *pEntry) 9.5 Porting LIBSE to a new target platform 9.5.1 Bu ilding the LIBSE library for SH3 target example 9.5.2 Building the HAL library for the target example 10 Sample Code 10.1 Sample code using the S1D13705 HAL API Page 10.2 Sample code without using the S1D13705 HAL API Page Page Page Page Page Page Page Page 10.3 Header Files The header files included here are the required for the HAL sample to compile correctly. Page Page Page Page Page Page Page S1D13705 Register Summary X27A-R-001-03 Page 1 01/02/13 S1D13705 Register Summary X27A-R-001-03 Page 13705CFG Configuration Program Document Number: X27A-B-001-03 Page Page Page 13705CFG Page 13705CFG Configuration Tabs General Tab Page Preferences Tab Clocks Tab Page Panel Tab Page Page Page Panel Powe r Tab Registers Tab 13705CFG Menus Open... Save Save As... Configure Multiple Export Enable Tooltips ERD on the Web About 13705CFG Page Page 13705SHOW Page Page Page Page Page 13705SPLT Page 13705SPLT Example Page Page Page 13705VIRT Page 13705VIRT Example Page Page Page 13705PLAY Page 13705PLAY Example Scripting Page Page Page Page 13705BMP This error message should never bee seen. Contact ERD. Page Page 13705PWR PC Platform Page Page Windows CE 2.x Display Drivers Document Number: X27A-E-001-03 Page WINDOWS CE 2.x DISPLAY DRIVERS Example Driver Builds Page Page Page Page Page Installation for CEPC Environment Configuration Compile Switches Mode File Page Page Page Page Wind River WindML v2.0 DISPLAY DRIVERS Building a WindML v2.0 Display Driver Page Page Wind River UGL v1.2 Display Drivers Document Number: X27A-E-003-02 Page Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Page Page Page Page Linux Console Driver Building the Console Driver for Linux Kernel 2.2.x Page Page Building the Console Driver for Linux Kernel 2.4.x Page Page Page Page Page QNX Photon v2.0 Display Driver Building the Photon v2.0 Display Driver Page Page Page Page S1D13XXX 32-Bit Windows Device Driver Installation Guide Driver Requirements Windows NT Version 4.0 Windows 2000 Windows 98/ME Windows 95 OSR2 Previous Versions of Windows 95 Page Page Page Page Page Page Page 1.1 Features 2 Installation and Configuration Page 3 LCD Interface Pin Mapping Table 3-1: LCD Signal Connector (J5) Pinout 4 CPU/Bus Interface Connector Pinouts Table 4-1: CPU/BUS Connector (H1) Pinout Table 4-2: CPU/BUS Connector (H2) Pinout 5 Host Bus Interface Pin Mapping Table 5-1: Host Bus Interface Pin Mapping 6 Technical Description 6.1 Embedded Memory Support 6.2 ISA Bus Support 6.2.1 Display Adapter Card Support 6.2.2 Expanded Memory Manager Support 6.3 Non-ISA Bus Support 6.4 Decoding Logic 6.5 Clock Input Support 6.6 LCD Panel Voltage Setting 6.7 Monochrome LCD Panel Support 6.8 Color Passive LCD Panel Support 6.9 Color TFT/D-TFD LCD Panel Support 6.10 Power Save Modes 6.11 Adjustable LCD Panel Negative Power Supply 6.12 Adjustable LCD Panel Positive Power Supply 6.13 CPU/Bus Interface Header Strips 7 Parts List Page 20 Epson Research and Development 8 Schematic Diagrams Figure 8-1: S1D13705B00C Schematic Diagram (1 of 4) Epson Research and Development Page 21 Figure 8-2: S1D13705B00C Schematic Diagram (2 of 4) Page 22 Epson Research and Development Figure 8-3: S1D13705B00C Schematic Diagram (3 of 4) Epson Research and Development Page 23 Figure 8-4: S1D13705B00C Schematic Diagram (4 of 4) Page Page Page Page Page Page Page Page 2 Features 3 Installation and Configuration 3.1 Configuration DIP Switches Table 3-1: Configuration DIP Switch Settings 3.2 Configuration Jumpers Page Page Page 4 CPU Interface 4.1 CPU Interface Pin Mapping Table 4-1: CPU Interface Pin Mapping 4.2 CPU Bus Connector Pin Mapping Table 4-2: CPU Bus Connector (H1) Pinout Page Page 18 Epson Research and Development 5 LCD Interface Pin Mapping 1These pin mappings use signal names commonly used for each panel type, however 2LCDPWR on J5 can be inverted by setting JP6 to 1-2. Table 5-1: LCD Signal Connector (J5) Pin Name Connector Pin No. 6 Technical Description 6.1 PCI Bus Support 6.2 Direct Host Bus Interface Support 6.3 S1D13705 Embedded Memory 6.4 Adjustable LCD Panel Positive Power Supply (VDDH) 6.5 Adjustable LCD Panel Negative Power Supply (VLCD) 6.6 Passive/Active LCD Panel Support 6.7 Power Save Modes 6.8 Clock Options 7 Software 8 References 9 Parts List Page Page 26 Epson Research and Development 10 Schematics Not Populated Figure 10-1: S1D13705B00C Schematics (1 of 5) Not Populated Epson Research and Development Page 27 Figure 10-2: S1D13705B00C Schematics (2 of 5) Page 28 Epson Research and Development Figure 10-3: S1D13705B00C Schematics (3 of 5) Epson Research and Development Page 29 Place close to PCIB pin 61 & 62Place close to PCIB pin 5 & 6 Place close to PCIA pin 2 S5U13705B00C Rev. 2.0 Evaluation Board User Manual S1D13705 Issue Date: 2002/09/16 X27A-G-014-02 Figure 10-4: S1D13705B00C Schematics (4 of 5) Page 30 Epson Research and Development Not Populated Place jumper to disable FPGA Figure 10-5: S1D13705B00C Schematics (5 of 5) FPGA configuration EPROM Page 12 Technical Support 12.1 EPSON LCD Controllers (S1D13705) Windows CE 3.x Display Drivers Document Number: X27A-E-006-01 Page WINDOWS CE 3.x DISPLAY DRIVERS Example Driver Builds Page Page Page Page Page Installation for CEPC Environment Configuration Compile Switches Mode File Resource Management Issues Page Page Page Page Page Page Page Page Page Page 2 Interfacing to the TMPR3912 Page Page 3.3 Generic #2 Interface Mode 4 Direct Connection to the Toshiba TMPR3912 4.1 General Description Figure 4-1: S1D13705 to TMPR3912 Direct Connection See Section 3.1 on page 9 and Section 3.3 on page 11 for Generic #2 pin descriptions. 4.2 Memory Mapping and Aliasing 4.3 S1D13705 Configuration 5 Using the ITE IT8368E PC Card Buffer 5.1 Hardware Description Figure 5-1: S1D13705 to TMPR3912 Connection Using an IT8368E IT8368E S1D13705 TMPR3912 5.2 IT8368E Configuration 5.3 Memory Mapping and Aliasing 5.4 S1D13705 Configuration Table 5-2: S1D13705 Configuration Using the IT8368E Table 5-1: TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E 6 Software 7.2 Toshiba MIPS TMPR3912 Processor 7.3 ITE IT8368E http://www.toshiba.com/taec/nonflash/indexproducts.html Page Page Page 1 S1D13705 Power Consumption 1.1 Conditions Table 1-1: S1D13705 Total Power Consumption 2 Summary Page Page Page Page Page Page Page Page 2 Interfacing to the MC68328 2.1 The MC68328 System Bus 2.2 Chip-Select Module 2.3 S1D13705 Host Bus Interface 2.3.1 Host Bus Pin Connection 2.3.2 Generic #1 Interface Mode 2.3.3 MC68K #1 Interface Mode 2.4 MC68328 To S1D13705 Interface 2.4.1 Hardware Description Page 2.4.2 S1D13705 Hardware Configuration 2.4.3 MC68328 Chip Select Configuration Page 3 Interfacing to the MC68EZ328 3.1 The MC68EZ328 System Bus 3.2 Chip-Select Module 3.3 S1D13705 Host Bus Interface 3.3.1 Host Bus Pin Connection 3.3.2 Generic #1 Interface Mode 3.4 MC683EZ28 To S1D13705 Interface 3.4.1 Hardware Description 3.4.2 S1D13705 Hardware Configuration 3.4.3 MC68EZ328 Chip Select Configuration Page 4 Interfacing to the MC68VZ328 4.1 The MC68VZ328 System Bus 4.2 Chip-Select Module 4.3 S1D13705 Host Bus Interface 4.3.1 Host Bus Pin Connection 4.3.2 Generic #1 Interface Mode 4.3.3 MC68K #1 Interface Mode 4.4 MC68VZ328 To S1D13705 Interface 4.4.1 Hardware Description Page 4.4.2 S1D13705 Hardware Configuration 4.4.3 MC68VZ328 Chip Select and Pin Configuration Page Page 7.2 Motorola Dragonball Processors Page Page Page Page Page Page Page 2 Interfacing to the NEC VR4102/VR4111 2.1 The NEC VR4102/VR4111 System Bus 2.1.2 LCD Memory Access Cycles Page Page 4 VR4102/VR4111 to S1D13705 Interface Page 4.3 NEC VR4102/VR4111 Configuration Page Page 7.2 NEC Electronics Inc. Page Page Page Page Page Page Page Page 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus 2.1.1 PC Card Overview 2.1.2 Memory Access Cycles Page Page Page 4 PC Card to S1D13705 Interface 4.1 Hardware Connections 4.3 Register/Memory Mapping Page Page 7.2 PC Card Standard Page Page Page Page Page Page Page 2 Interfacing to the MPC821 2.1 The MPC8xx System Bus 2.2 MPC821 Bus Overview 2.2.1 Normal (Non-Burst) Bus Transactions 2.2.2 Burst Cycles 2.3 Memory Controller Module 2.3.1 General-Purpose Chip Select Module (GPCM) 2.3.2 User-Programmable Machine (UPM) 3.1 Host Bus Interface Modes 3.2 Generic #1 Host Bus Interface Mode 4 MPC821 to S1D13705 Interface 4.2 MPC821ADS Evaluation Board Hardware Connections Table 4-1: List of Connections from MPC821ADS to S1D13705 (Continued) 4.3 S1D13705 Hardware Configuration 4.4 MPC821 Chip Select Configuration 4.5 Test Software Page Page Page 7.1 EPSON LCD/CRT Controllers (S1D13705) 7.2 Motorola MPC821 Processor Page Page Page Page Page Page Page 2 Interfacing to the MCF5307 2.1 The MCF5307 System Bus 2.1.2 Normal (Non-Burst) Bus Transactions 2.1.3 Burst Cycles 2.2 Chip-Select Module Page Page 4 MCF5307 To S1D13705 Interface Page 4.3 MCF5307 Chip Select Configuration Page Page 7.2 Motorola MCF5307 Processor Page Page Page Page Page Page Page 2 Interfacing to the PR31500/PR31700 Page Page 3.3 Generic #2 Interface Mode 4 Direct Connection to the Philips PR31500/PR31700 4.1 General Description Figure 4-1: S1D13705 to PR31500/PR31700 Direct Connection See Section 3.1 on page 9 and Section 3.3 on page 11 for Generic #2 pin descriptions. 4.2 Memory Mapping and Aliasing 4.3 S1D13705 Configuration and Pin Mapping 5 Using the ITE IT8368E PC Card Buffer 5.1 Hardware Description Page 5.2 IT8368E Configuration 5.3 Memory Mapping and Aliasing 5.4 S1D13705 Configuration 6 Software 7.2 Philips MIPS PR31500/PR31700 Processor 7.3 ITE IT8368E Page Page Table of Contents Page Page Page 1 Introduction 1.1 General Description 2 S1D13704/5 Bus Interface 2.1 Bus Interface Modes 2.2 Generic #2 Interface Mode 3 TMPR3912/22U and S1D13704/5 Interface 3.1 Hardware Connections Figure 3-1: S1D13704 to TMPR3912/22U Interface 3.2 Memory Mapping and Aliasing 3.3 S1D13704/5 Configuration and Pin Mapping 4 CPU Module Description 4.1 Clock Signals 4.1.1 BUSCLK 4.1.2 CLKI 4.2 LCD Connectors 4.2.1 50-pin LCD Module Connector, J3 4.2.2 Standard Epson LCD Connector, J4 4.3 LCD Controller 4.3.1 S1D13704 vs. S1D13705 4.3.2 LCDPWR Polarity 4.3.3 S1D13704\75 Chip Select Page Page Page Page Page Page Page Page 2 Interfacing to the NEC VR4181A 2.1 The NEC VR4181A System Bus 2.1.2 LCD Memory Access Signals Page Page 4 VR4181A to S1D13705 Interface Figure 4-1: Typical Implementation of VR4181A to S1D13705 Interface Page 4.3 NEC VR4181A Configuration Page Page 7.2 NEC Electronics Inc. Page Page Page Page Page Page Page Page 2 Interfacing to an 8-bit Processor 2.1 The Generic 8-bit Processor System Bus Page Page 4 8-Bit Processor to S1D13705 Interface 4.3 Register/Memory Mapping Page Page 7.1 Epson LCD/CRT Controllers (S1D13705)