Epson S1D13705 technical manual PC Card Read Cycle

Epson Research and Development		Page 5
Vancouver Design Center
	List of Tables
Table 3-1:	Host Bus Interface Pin Mapping	10
Table 4-1:	Summary of Power-On/Reset Options	13
Table 4-2:	Host Bus Interface Selection	13

List of Figures

Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4-1: Typical Implementation of PC Card to S1D13705 Interface . . . . . . . . . . . . . . . . 12

Interfacing to the PC Card Bus	S1D13705
Issue Date: 01/02/13	X27A-G-009-02