Epson S1D13705 technical manual 3 MC68VZ328 Chip Select and Pin Configuration

Epson Research and Development	Page 29
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4.4.3 MC68VZ328 Chip Select and Pin Configuration

The S1D13705 requires a 128K byte address space for the display buffer and its internal registers. To accommodate this block size, it is preferable (but not required) to use one of the chip selects from groups A or B. Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes. Therefore, any chip select other than CSA0 would be suitable for the S1D13705 interface.

In the example interface, chip select CSB1 is used to control the S1D13705. A 128K byte address space is used with the S1D13705 control registers mapped into the top 32 bytes of the 128K byte block and the 80K bytes of display buffer mapped to the starting address of the block. The chip select should have its RO (Read Only) bit set to 0, its BSW (Bus Data Width) set to 1 for a 16-bit bus, and the WS (Wait states) bit should be set to 111b to allow the S1D13705 to terminate bus cycles externally with DTACK. Enable DTACK pin function with Register FFFFF433, Port G Select Register, bit 0.

Additional registers must be configured if the M68K #1 host bus interface is used. LDS, UDS and R/W must be enabled by setting register FFFFFF443h bits 1, 2, and 3 to zero to enable the internal 68000 pin functions.

Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors	S1D13705
Issue Date: 01/02/13	X27A-G-007-04