Epson technical manual S1D13705 Internal Clock Requirements

Epson Research and Development	Page 85
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13.6 Clock Requirements

The following table shows what clock is required for which function in the S1D13705

Table 13-5: S1D13705 Internal Clock Requirements

Function	BCLK	CLKI
	Is required during register accesses. BCLK
	can be shut down between accesses: allow
	eight BCLK pulses plus 12 MCLK pulses
Register Read/Write	(8TBCLK + 12TMCLK) after the last access	Not Required
	before shutting BCLK off. Allow one BCLK
	pulse after starting up BCLK before the next
	access
	Is required during memory accesses. BCLK
	can be shut down between accesses: allow
	eight BCLK pulses plus 12 MCLK pulses
Memory Read/Write	(8TBCLK + 12TMCLK) after the last access	Required
	before shutting BCLK off. Allow one BCLK
	pulse after starting up BCLK before the next
	access
	Is required during LUT register accesses.
	BCLK can be shut down between accesses:
Look-Up Table Register	allow eight BCLK pulses plus 12 MCLK
	pulses (8TBCLK + 12TMCLK) after the last	Not Required
Read/Write
	access before shutting BCLK off. Allow one
	BCLK pulse after starting up BCLK before
	the next access
		Can be stopped after 128 frames from
Software Power Save	Required	entering Software Power Save, i.e. after
		REG[03h] bits 1-0 = 11
Hardware Power Save	Not Required	Can be stopped after 128 frames from
		entering Hardware Power Save

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10