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Epson Research and Development

 

Vancouver Design Center

 

 

2 Features

2.1Integrated Frame Buffer

Embedded 80K byte SRAM display buffer.

2.2CPU Interface

Direct support of the following interfaces: Hitachi SH-3.

Hitachi SH-4. Motorola M68K.

MPU bus interface using WAIT# signal.

Direct memory mapping of internal registers.

Single level CPU write buffer.

Registers are mapped into upper 32 bytes of 128K byte address space.

The complete 80K byte display buffer is directly and contiguously available through the 17-bit address bus.

2.3Display Support

4/8-bit monochrome LCD interface.

4/8-bit color LCD interface.

Single-panel, single-drive passive displays.

Dual-panel, dual-drive passive displays.

Active Matrix TFT / D-TFD interface

Register level support for EL panels.

Example resolutions:

640x480 at a color depth of 2 bpp

640x240 at a color depth of 4 bpp

320x240 at a color depth of 8 bpp

S1D13705

Hardware Functional Specification

X27A-A-001-10

Issue Date: 02/02/01

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Epson S1D13705 Features, Integrated Frame Buffer, CPU Interface, Display Support, Embedded 80K byte Sram display buffer