Epson S1D13705 technical manual Direct Connection to the Philips PR31500/PR31700

Page 12 Epson Research and Development

Vancouver Design Center

4 Direct Connection to the Philips PR31500/PR31700

4.1 General Description

In this example implementation the S1D13705 occupies the PR31500/PR31700 PC Card slot #1.

The S1D13705 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The address bus of the PR31500/PR31700 PC Card interface is multiplexed and must be demultiplexed using an advanced CMOS latch (e.g., 74AHC373). The direct connection approach makes use of the S1D13705 in its “Generic #2” interface configuration.

The following diagram demonstrates a typical implementation of the interface.

				S1D13705
PR31500/PR31700			+3.3V	IO VDD, CORE VDD
/CARDIOREAD				RD#
/CARDIOWR				WE0#
/CARD1CSL				WE1#
/CARD1CSH
			+3.3V	BS#
			+3.3V	RD/WR#
ENDIAN			System RESET	RESET#
Latch				CS#
ALE
A[12:0]				AB[16:13]
				AB[12:0]
D[31:24]				DB[7:0]
D[23:16]				DB[15:8]
VDD	pull-up
/CARD1WAIT				WAIT#
DCLKOUT			See text	CLKI
Clock divider		...or...	Oscillator	BCLK

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 4-1: S1D13705 to PR31500/PR31700 Direct Connection

Note

See Section 3.1 on page 9 and Section 3.3 on page 11 for Generic #2 pin descriptions.

S1D13705	Interfacing to the Philips MIPS PR31500/PR31700 Processor
X27A-G-012-02	Issue Date: 01/02/13