Epson S1D13705 7.2 Clock Input Requirements

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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.2 Clock Input Requirements
Figure 7-7: Clock Input Requirements for CLKI
Note
When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1.
Table 7-7: Clock Input Requirements for CLKI
Symbol Parameter Min Max Units
fCLKI Input Clock Frequency (CLKI) 50 MHz
TCLKI Input Clock period (CLKI) 1/fCLKI ns
tPWH Input Clock Pulse Width High (CLKI) 8 ns
tPWL Input Clock Pulse Width Low (CLKI) 8 ns
tfInput Clock Fall Time (10% - 90%) 5 ns
trInput Clock Rise Time (10% - 90%) 5 ns
tPWL tPWH
tf
Clock Input Waveform
tr
TCLKI
VIH
VIL
10%
90%