Epson S1D13705 Clock Input Requirements, Input Clock Frequency Clki MHz, Input Clock period Clki

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7.2 Clock Input Requirements

Clock Input Waveform

tPWH	tPWL
90%
VIH
VIL
10%
tr	t f
	TCLKI

Figure 7-7: Clock Input Requirements for CLKI

Table 7-7: Clock Input Requirements for CLKI

Symbol	Parameter	Min	Max	Units
fCLKI	Input Clock Frequency (CLKI)		50	MHz
TCLKI	Input Clock period (CLKI)	1/fCLKI		ns
tPWH	Input Clock Pulse Width High (CLKI)	8		ns
tPWL	Input Clock Pulse Width Low (CLKI)	8		ns
tf	Input Clock Fall Time (10% - 90%)		5	ns
tr	Input Clock Rise Time (10% - 90%)		5	ns

Note

When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1.

S1D13705	Hardware Functional Specification
X27A-A-001-10	Issue Date: 02/02/01