Page 10

Epson Research and Development

 

Vancouver Design Center

 

 

The S1D13705 has 4 configuration inputs (CONF[3:0]) and BS# input, which are read on the rising edge of RESET#. All S1D13705 configuration inputs and BS# input are fully configurable using a six position DIP switch as described below and a jumper for BS#.

Table 3-1: Configuration DIP Switch Settings

Switch

S1D13705

Value on this pin at rising edge of RESET# is used to configure:

Signal

 

Open (Off/1)

 

Closed (On/0)

 

 

 

 

 

 

 

 

 

 

 

Select host bus interface as follows:

 

 

 

CNF2 CNF1

CNF0

Host Bus Interface

 

 

0

0

0

SH-4

 

 

0

0

1

SH-3

 

 

0

1

0

Reserved

SW1-[3:1]

CNF[2:0]

0

1

1

MC68K #1

 

 

1

0

0

Reserved

 

 

1

0

1

MC68K #2

 

 

1

1

0

Reserved

 

 

 

 

 

 

 

 

1

1

1

Generic #1/Generic #21

 

 

Note: The host bus interface is 16-bit.

 

 

 

 

 

 

SW1-4

CNF3

Big Endian bus interface

 

Little Endian bus interface

SW1-5

Not Used

Not Used

 

 

 

 

 

 

 

 

SW1-6

GPIO0

Hardware Suspend Enable

 

Hardware Suspend Disable

 

 

 

 

 

 

= Required settings when used with PCI Bridge FPGA

Note

1The selection between Generic #1 and Generic #2 is made with JP3.

S1D13705

S5U13705B00C Rev. 2.0 Evaluation Board User Manual

X27A-G-014-02

Issue Date: 2002/09/16

Page 322
Image 322
Epson S1D13705 technical manual SH-4, SH-3, Big Endian bus interface Little Endian bus interface SW1-5, Not Used SW1-6