Epson S1D13705 technical manual List of Tables

Epson Research and Development		Page 5
Vancouver Design Center
	List of Tables
Table 3-1:	Host Bus Interface Pin Mapping	13
Table 4-1:	List of Connections from MPC821ADS to S1D13705	16
Table 4-2: Configuration Settings		18
Table 4-3:	Host Bus Selection	18

List of Figures

Figure 2-1:	Power PC Memory Read Cycle	. . . . . . . . . . . . . . . 9
Figure 2-2:	Power PC Memory Write Cycle	. . . . . . . . . . . . . . . 10
Figure 4-1:	Typical Implementation of MPC821 to S1D13705 Interface	. . . . . . . . . . . . . . . 15

Interfacing to the Motorola MPC821 Microprocessor	S1D13705
Issue Date: 01/02/13	X27A-G-010-02