Epson S1D13705 technical manual T6a T6b T7a T14 T11

Epson Research and Development	Page 45
Vancouver Design Center

Sync Timing

Frame Pulse

Line Pulse

Data Timing

Line Pulse

Shift Pulse 2

Shift Pulse

FPDAT[7:0]

	t1	t2
	t4			t3
t6a
t6b		t8			t9
t7a	t14			t11	t10
	t7b
	t12	t13 t12		t13
		1	2

Figure 7-18: Single Color 8-Bit Panel A.C. Timing (Format 1)

Table 7-14: Single Color 8-Bit Panel A.C. Timing (Format 1)

Symbol		Parameter	Min	Typ	Max	Units
	t1	Frame Pulse setup to Line Pulse falling edge	note 2			(note 1)
	t2	Frame Pulse hold from Line Pulse falling edge	9			Ts
	t3	Line Pulse period	note 3
	t4	Line Pulse pulse width	9			Ts
	t6a	Shift Pulse falling edge to Line Pulse rising edge	note 4
	t6b	Shift Pulse 2 falling edge to Line Pulse rising edge	note 5
	t7a	Shift Pulse 2 falling edge to Line Pulse falling edge	note 6
	t7b	Shift Pulse falling edge to Line Pulse falling edge	note 7
	t8	Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge	t14 + 2			Ts
	t9	Shift Pulse 2, Shift Pulse period	4			Ts
	t10	Shift Pulse 2, Shift Pulse pulse width low	2			Ts
	t11	Shift Pulse 2, Shift Pulse pulse width high	2			Ts
	t12	FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge	1			Ts
	t13	FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge	1			Ts
	t14	Line Pulse falling edge to Shift Pulse rising edge	25			Ts
1.	Ts	= pixel clock period
2.	t1min	= t3min - 9Ts
3.	t3min	= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
4.	t6amin	= [(REG[08h] bits 4-0) x 8]Ts
5.	t6bmin	= [(REG[08h] bits 4-0) x 8 + 2]Ts
6.	t7amin	= [(REG[08h] bits 4-0) x 8 + 11]Ts
7.	t7bmin	= [(REG[08h] bits 4-0) x 8 + 11] - t10]Ts

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10