Epson Research and Development

Page 5

Vancouver Design Center

 

 

 

 

 

List of Tables

 

Table 3-1:

Host Bus Interface Pin Mapping

12

Table 4-1:

Summary of Power-On/Reset Options

15

Table 4-2:

Host Bus Selection

15

 

List of Figures

Figure 2-1:

NEC VR4102/VR4111 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4-1:

Typical Implementation of VR4102/VR4111 to S1D13705 Interface . . . . . . . . . . . 14

Interfacing to the NEC VR4102/VR4111 Microprocessor

S1D13705

Issue Date: 01/02/13

X27A-G-008-02

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Image 423
Epson S1D13705 technical manual List of Tables, NEC VR4102/VR4111 Read/Write Cycles