Epson Research and Development

Page 3

Vancouver Design Center

 

 

 

Table of Contents

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2Interfacing to the NEC VR4102/VR4111 . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 The NEC VR4102/VR4111 System Bus . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.2LCD Memory Access Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

S1D13705 Host Bus Interface

12

 

3.1

Host Bus Pin Connection

12

 

3.2

Generic #2 Interface Mode

13

4

VR4102/VR4111 to S1D13705 Interface

14

 

4.1

Hardware Description

14

4.2S1D13705 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . 15

 

4.3

NEC VR4102/VR4111 Configuration

16

5

Software

17

6

References

18

 

6.1

Documents

18

 

6.2

Document Sources

18

7

Technical Support

19

7.1Epson LCD Controllers (S1D13705) . . . . . . . . . . . . . . . . . . . . . 19

7.2NEC Electronics Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interfacing to the NEC VR4102/VR4111 Microprocessor

S1D13705

Issue Date: 01/02/13

X27A-G-008-02

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Image 421
Epson S1D13705 Introduction Interfacing to the NEC VR4102/VR4111, Host Bus Pin Connection Generic #2 Interface Mode