Epson S1D13705 technical manual Pin Name Type Pin # Cell

Page 20	Epson Research and Development
	Vancouver Design Center

Pin Names	Type	Pin #	Cell	RESET#		Description
				State
					This pin has multiple functions.
					• For SH-3/SH-4 mode, this pin inputs the read signal (RD#).
					•	For MC68K #1, this pin must be tied to IO VDD.
					• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
RD#	I	76	CS	Input	•	For Generic #1, this pin inputs the read command for the
						lower data byte (RD0#).
					• For Generic #2, this pin inputs the read command (RD#).
					See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22for
					summary.
					This pin has multiple functions.
					• For SH-3 mode, this pin outputs the wait request signal
						(WAIT#).
					• For SH-4 mode, this pin outputs the device ready signal
						(RDY#).
					• For MC68K #1, this pin outputs the data transfer
WAIT#	O	2	TS2	Hi-Z		acknowledge signal (DTACK#).
					• For MC68K #2, this pin outputs the data transfer and size
						acknowledge bit 1 (DSACK1#).
					• For Generic #1, this pin outputs the wait signal (WAIT#).
					• For Generic #2, this pin outputs the wait signal (WAIT#).
					See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22for
					summary.
RESET#	I	73	CS	0	Active low input to set all internal registers to the default state and
					to force all signals to their inactive states.
5.2.2 LCD Interface

Pin Name	Type	Pin #	Cell	RESET#		Description
				State
		30, 31, 32,
FPDAT[7:0]	O	33, 34, 35,	CN3	0	Panel Data
		36, 37
					These pins have multiple functions.
					• Panel Data bits [10:8] for TFT/D-TFD panels.
FPDAT[10:8]	O,	24, 25, 26	CN3	Input	• General Purpose Input/Output pins GPIO[3:1].
	IO				These pins should be connected to IO VDD when unused.
					See Table 5-3: “LCD Interface Pin Mapping,” on page 23for
					summary.
					This pin has multiple functions.
					•	Panel Data bit 11 for TFT/D-TFD panels.
	O,				•	General Purpose Input/Output pin GPIO4.
FPDAT11		23	CN3	Input	• Inverse Video select pin.
	IO
					This pin should be connected to IO VDD when unused. See
					Table 5-3: “LCD Interface Pin Mapping,” on page 23for
					summary.
FPFRAME	O	39	CN3	0	Frame Pulse

S1D13705	Hardware Functional Specification
X27A-A-001-10	Issue Date: 02/02/01