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Epson Research and Development

Vancouver Design Center

7.1.2 SH-3 Interface Timing

 

TCKIO

t2

t3

 

 

CKIO

 

 

 

 

 

 

 

t4

 

 

t5

A[16:0], M/R#

 

 

 

 

 

RD/WR#

 

 

 

 

 

 

 

t6

t7

 

 

BS#

 

 

 

 

 

 

 

t8

 

 

 

CSn#

 

 

 

 

 

 

 

 

t9

t10

t11

 

 

 

 

 

WEn#

 

 

 

 

 

RD#

 

 

 

 

 

 

 

 

t12

t13

 

WAIT#

Hi-Z

 

 

 

Hi-Z

 

 

 

 

 

 

 

 

 

t14

t15

D[15:0]

Hi-Z

 

 

 

Hi-Z

(write)

 

 

 

 

 

 

 

 

 

 

 

 

t16

t17

D[15:0]

Hi-Z

 

 

VALID

Hi-Z

(read)

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 7-2: SH-3 Bus Timing

 

Note

The SH-3 Wait State Control Register for the area in which the S1D13705 resides must be set to a non-zero value.

S1D13705

Hardware Functional Specification

X27A-A-001-10

Issue Date: 02/02/01

Page 34
Image 34
Epson S1D13705 technical manual 2 SH-3 Interface Timing, T12 T13, T14 T15 D150, Write T16 T17 D150