Epson Research and Development

Page 5

Vancouver Design Center

 

 

 

 

 

List of Tables

 

Table 3-1:

Host Bus Interface Pin Mapping

10

Table 4-1:

Summary of Power-On/Reset Options

13

Table 4-2:

Host Bus Selection

13

List of Figures

Figure 4-1: Typical Implementation of VR4181A to S1D13705 Interface . . . . . . . . . . . . . . . 12

Interfacing to the NEC VR4181A™ Microprocessor

S1D13705

Issue Date: 01/02/13

X27A-G-013-02

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Image 533
Epson technical manual Typical Implementation of VR4181A to S1D13705 Interface