Epson technical manual S1D13705 Power Consumption

Epson Research and Development	Page 3
Vancouver Design Center

1 S1D13705 Power Consumption

S1D13705 power consumption is affected by many system design variables.

•Input clock frequency (CLKI): the CLKI frequency and the internal clock divide register deter- mine the operating clock (CLK) frequency of the S1D13705. The higher CLK is, the higher the frame fate, performance, and power consumption.

•CPU interface: the S1D13705 current consumption depends on the BUSCLK frequency, data width, number of toggling pins, and other factors – the higher the BUSCLK, the higher the CPU performance and power consumption.

•VDD voltage levels (Core and IO): the voltage level of the Core and IO sections in the S1D13705 affects power consumption – the higher the voltage, the higher the consumption.

•Display mode: the resolution, panel type, and color depth affect power consumption. The higher the resolution/color depth and number of LCD panel signals, the higher the power consumption.

Note

If the High Performance option is turned on, the power consumption increases to that of 8 bit-per-pixel mode for all color depths.

There are two power save modes in the S1D13705: Software and Hardware Power Save. The power consumption of these modes is affected by various system design variables.

•CPU bus state during Power Save: the state of the CPU bus signals during Power Save has a substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.) reduces overall system power consumption.

•CLKI state during Power Save: disabling the CLKI during Power Save has substantial power savings.

Power Consumption	S1D13705
Issue Date: 01/02/13	X27A-G-006-02