Epson technical manual S1D13705B00C Schematic Diagram 1 of 4

Epson Research and Development			Page 5
Vancouver Design Center
	List of Tables
Table 2-1: Configuration DIP Switch Settings		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2-2:	Host Bus Selection	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2-3:	Jumper Settings	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-1: LCD Signal Connector (J5) Pinout		. . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Table 4-1: CPU/BUS Connector (H1) Pinout .		. . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Table 4-2: CPU/BUS Connector (H2) Pinout .		. . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Table 5-1:	Host Bus Interface Pin Mapping . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . .	13

List of Figures

Figure 8-1: S1D13705B00C Schematic Diagram (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8-2: S1D13705B00C Schematic Diagram (2 of 4) . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8-3: S1D13705B00C Schematic Diagram (3 of 4) . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8-4: S1D13705B00C Schematic Diagram (4 of 4) . . . . . . . . . . . . . . . . . . . . . . . 23

S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual	S1D13705
Issue Date: 01/02/13	X27A-G-005-03