Configuration Jumpers, Jumper Summary | Epson S1D13705 specs

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3.2 Configuration Jumpers

The S5U13705B00C has six jumper blocks which configure various setting on the board. The jumper positions for each function are shown below.

Table 3-2: Jumper Summary

	Jumper	Function	Position 1-2	Position 2-3	No Jumper

	JP1	IOVDD Selection	+3.3V IOVDD	+5.0V IOVDD	n/a

	JP2	Bus Clock Selection	External Oscillator (U7)	From Host CPU	n/a
	JP3	BS# Signal Selection	Pulled Down to GND (for	Pulled High to IOVDD (for	For SH-3, SH-4, MC68k #1
	JP3	BS# Signal Selection	Generic #1 Interface)	Generic #2 Interface)	and MC68K #2 bus
			Generic #1 Interface)	Generic #2 Interface)	and MC68K #2 bus
	JP4	LCD Panel Voltage Selection	+3.3V LCDVCC	+5.0V LCDVCC	n/a

	JP5	PCI Bridge FPGA	Disabled for non-PCI host	n/a	Enabled for PCI host
	JP6	LCDPWR Polarity	Active Low	Active High	n/a

	JP7	CLKI Selection	External Oscillator (U2)	BCLK	n/a

= Required settings when used with PCI Bridge FPGA

JP1 - IOVDD Selection

JP1 selects the IOVDD voltage for S1D13705.

When the jumper is in position 1-2, IOVDD is 3.3V. This settings must be used for a 3.3V host CPU system.

When the jumper is in position 2-3, IOVDD is 5.0V. This setting must be used for a 5.0V host CPU system.

Note

For PCI host, JP1 can be set in either position.

JP1

3.3 Volt	5.0 Volt
IOVDD	IOVDD

Figure 3-2: Configuration Jumper (JP1) Location

S5U13705B00C Rev. 2.0 Evaluation Board User Manual	S1D13705
Issue Date: 2002/09/16	X27A-G-014-02

Image 323

Epson S1D13705 technical manual Configuration Jumpers, Jumper Summary, Jumper Function Position No Jumper, PCI Bridge Fpga

Contents

Document No. X27A-Q-001-04 S1D13705 This page Left Blank Customer Support Information This page Left Blank February S1D13705 Embedded Memory LCD Controller Embedded 80K byte Sram display buffer Software Suspend mode LCD power-down sequencing Document Number X27A-A-001-10 Hardware Functional Specification This page Left Blank Table of Contents Mechanical Data Power Save ModesRegisters SwivelView List of Tables This page Left Blank List of Figures 2 Bit-per-pixel Monochrome Mode Data Output Path Overview Description IntroductionScope Display Support FeaturesIntegrated Frame Buffer CPU Interface Package Display ModesClock Source Miscellaneous Typical System Diagram SH-4 Bus Typical System Implementation Diagrams Typical System Diagram M68K #1 Bus Typical System Diagram Generic #1 Bus Memory Controller Functional Block DiagramFunctional Block Descriptions Host Interface LCD Interface Power SavePower Save contains the power save mode circuitry Look-Up Table Package type 80 pin surface mount QFP14 PinsPinout Diagram Description Pin DescriptionKey Pin Names Type Pin # Cell For the lower data byte WE0# For SH-3/SH-4 mode, this pin inputs the write enable signalInput This pin inputs the chip select signal For MC68K #1, this pin inputs the R/W# signal Pin Name Type Pin # Cell Pin Name Type Pin # Driver Description Power SupplyClock Input Miscellaneous Host Bus Interface Pin Mapping Summary of Configuration OptionsSummary of Power On/Reset Options Host Bus Interface Pin Mapping Bit Pin Name Bit Dual Single 12-bit Format LCD Interface Pin MappingLCD Interface Pin Mapping Recommended Operating Conditions for Core VDD = 3.3V ± 10% C. CharacteristicsInput Specifications Absolute Maximum Ratings Output Specifications 1 SH-4 Interface Timing Bus Interface Timing T11 Rising edge CSn# to RDY# high impedance Symbol Parameter Min Max UnitsBus Clock frequency MHz Bus Clock period Write T16 T17 D150 2 SH-3 Interface TimingT12 T13 T14 T15 D150 Symbol Parameter Min Maxa Units UDS#, LDS# falling edge to D150 valid write cycle Motorola MC68K #1 Interface TimingAS# high to DTACK# high AS# high to DTACK# high impedance AS#, DS# rising edge to D3116 high impedance Motorola MC68K #2 Interface TimingAS# high to DSACK1# high AS# high to DSACK1# high impedance DS# falling edge to D3116 valid write cycle Generic #1 Timing Generic #1 Interface Timing Generic #2 Timing Generic #2 Interface Timing Input Clock Pulse Width High Clki Clock Input RequirementsInput Clock Frequency Clki MHz Input Clock period Clki Input Clock Pulse Width High Bclk Input Clock Frequency Bclk MHzInput Clock period Bclk REG03h to FPLINE, FPFRAME, FPSHIFT, FPDAT, Drdy Power On/Reset TimingSymbol Parameter Min Typ Max Units Display Interface Active Inactive Power Down/Up TimingLcdpwr Override REG03h bit HW Power Save REG03h bits FP Signals Active Inactive 11 Single Monochrome 4-Bit Panel Timing Single Monochrome 4-Bit Panel Timing Data Timing Sync Timing 13 Single Monochrome 8-Bit Panel Timing Single Monochrome 8-Bit Panel Timing = REG08h bits 4-0 x 8 + 4Ts 15 Single Color 4-Bit Panel Timing Single Color 4-Bit Panel Timing = REG08h bits 4-0 x 8 + 1.5Ts 17 Single Color 8-Bit Panel Timing Format Single Color 8-Bit Panel Timing Format T6a T6b T7a T14 T11 19 Single Color 8-Bit Panel Timing Format = REG08h bits 4-0 x 8 + 1Ts 21 Dual Monochrome 8-Bit Panel Timing Dual Monochrome 8-Bit Panel Timing = REG04h bits 6-0+1 x 8 + REG08h bits 4-0 + 4 x 8 x 2Ts 23 Dual Color 8-Bit Panel Timing Dual Color 8-Bit Panel Timing = REG08h bits 4-0 x 2x 8 + 17Ts 25 12-Bit TFT/D-TFD Panel Timing 10 9/12-Bit TFT/D-TFD Panel Timing 26 TFT/D-TFD A.C. Timing 18 TFT/D-TFD A.C. Timing Bit RegistersRegister Mapping Register Descriptions Don’t care Active highPanel Data Format Color/Mono Dual/Single Data Width Bit Function High Performance BPP Bit Display Modes Gray Scale/Color Mode SelectionColor/Mono Bit-Per-Pixel Bit Display Mode High Performance Selection Video data is inverted after the Look-Up Table Video Mode Select Options belowInverse Video Mode Select Options Software Power Save Mode Selection Hardware Power Save/GPIO0 Operation Size Bit This register must not be set to a value less than 03hVertical Panel Fpline Start Following constraint must be satisfied MOD Rate Bit Vertical Non Screen 2 Start Screen 1 Start Vertical Size Bit MemoryOffset Bit LUT Address Screen-Register Relationship, Split Screen LUT Data Bit REG18h Gpio Configuration Control Register SwivelView Mode Enable Mode Select Selection of SwivelView Mode Where CLK is Clki REG02h bit 4 = 0 or CLKI/2 REG02h bit 4 = Selection of Pclk and Mclk in SwivelView ModeCreate a virtual image in SwivelView mode Pixel Clock Pclk Select Mode Enable Mode Select TFT/D-TFD and Passive Single-Panel modes Passive Dual-Panel modeFrame Rate Calculation 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Display Data Formats Green Look-Up Table LUT is used for all monochrome modes Bit-per-pixel Monochrome modeLook-Up Table Architecture Monochrome Modes 4 Bit-per-pixel Monochrome Mode Data Output Path Color Modes Bit-per-pixel Color Mode 2 Bit-per-pixel Color Mode Data Output Path 4 Bit-per-pixel Color Mode Data Output Path 8 Bit-per-pixel Color Mode Data Output Path SwivelView Default SwivelView Mode Where bpb is bits-per-byte and bpp is bits-per-pixel How to Set Up Default SwivelView ModeWhere bpp is bits-per-pixel and bpb is bits-per-byte Start Address 480 Image refreshed by S1D13705 Alternate SwivelView Mode How to Set Up Alternate SwivelView Mode Default SwivelView Mode Alternate SwivelView Mode Comparison Between Default and Alternate SwivelView ModesSwivelView Mode Limitations Default and Alternate SwivelView Mode Comparison Hardware Power Save Mode Power Save ModesSoftware Power Save Mode Hardware Software Normal Power Save Mode Function SummaryPanel Power Up/Down Sequence Power Save Mode Function Summary Software Power Save Turning Off Bclk Between Accesses S1D13705 Internal Clock Requirements Clock Requirements 125 Mechanical DataQFP14 80 pin Unit mm 14.0 ± 12.0 ± Index Japan North America Taiwan Sales and Technical Support This page Left Blank Document Number X27A-G-002-03 Programming Notes and Examples This page Left Blank Look-Up Table LUT LCD Power Sequencing and Power Save ModesIntroduction Initialization Memory Models Sample Code Identifying the S1D13705 Hardware Abstraction Layer HAL S1D13705 Initialization Sequence This page Left Blank Introduction Register Values InitializationDisplay Buffer Location Register Value hex See Also Frame Rate CalculationS1D13705 Initialization Sequence = Horizontal Non-Display Period in pixels Where Pclk = Pixel clock in HzFor a dual passive panel the formula is = Horizontal Display Period in pixels Epson Research and Development Bit Pixel Memory Models1 Bit-Per-Pixel 2 Colors/Gray Shades Pixel Bit 2 Bit-Per-Pixel 4 Colors/Gray Shades4 Bit-Per-Pixel 16 Colors/Gray Shades Green bit Eight Bit-Per-Pixel 256 Colors Look-Up Table LUT LUT Data Look-Up Table Registers Unused entries Look-Up Table OrganizationColor Modes Index Red Green Blue Indicates unused entries Example LUT Values for 2 Bpp Color Mode Bpp color Index Index Address Red Green Blue Gray Shade ModesRecommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade Suggested LUT Values for 4 Bpp Gray Shade Virtual Display Advanced Techniques Offset RegistersExamples REG11h Memory Address Offset Register Panning and Scrolling REG10h Screen 1 Display Start Address 2 MSB Number of Pixels Panned Using Start AddressREG0Ch Screen 1 Display Start Address 0 LSB REG0Dh Screen 1 Display Start Address 1 MSB Panning to the left To scroll down 320x240 Single Panel For Split Screen Split Screen REG13 Screen 1 Vertical Size MSB REG12 Screen 1 Vertical Size LSB REG0Fh Screen 2 Display Start Address 1 MSB REG0Eh Screen 2 Display Start Address 0 LSB Examples Hardware Software Power Save Override Enable Bit LCD Power Sequencing and Power Save ModesLCD Power Sequencing REG03h Mode Register LCD Enable/Disable Introduction To Hardware Rotation Default Portrait ModeHardware Rotation Portrait Alternate Portrait Mode REG0Eh Screen 1 Start Word Address MSB REG1Bh Portrait Mode RegisterREG0Ch Screen 1 Start Word Address LSB REG0Dh Screen 1 Start Word Address MSB Epson Research and Development Limitations Default and Alternate Portrait Mode ComparisonDefault Portrait Mode Alternate Portrait Mode Power of 2. In most cases, a virtual Examples Vancouver Design Center 16 , 000 FrameRate Vancouver Design Center Identifying the S1D13705 Introduction Contents of the HalstructHardware Abstraction Layer HAL Function Description Using the HAL libraryAPI for 13705HAL Register / Memory Access SeSetInit InitializationInt seRegisterDeviceconst Lphalstruc lpHalInfo Int seGetIdint * pId General HAL Support Int seGetBytesPerScanlineint * pBytes Int seSetBitsPerPixelint BitsPerPixelInt seGetBitsPerPixelint * pBitsPerPixel Int seGetLastUsableBytelong * plLastByte Int seDelayint MilliSecondsInt seGetScreenSizeint * Width, int * Height Int seSetHWRotateint Rotate Advanced HAL FunctionsInt seSetHighPerformanceBOOL OnOff Int seSetPortraitMethod int Style Int seSplitScreenint Screen, int VisibleScanlines Int seSplitInitWORD Scrn1Addr, Word Scrn2Addr SeVirtInit must be been called before calling seVirtMove Int seVirtInitDWORD VirtX, Dword * VirtYInt seVirtMoveint Screen, int x, int y Int seReadDisplayByteDWORD Offset, Byte *pByte Register / Memory AccessInt seGetRegint Index, Byte * pValue Int seSetRegint Index, Byte Value Int seWriteDisplayBytesDWORD Offset, Byte Value, Dword Count Int seReadDisplayDwordDWORD Offset, Dword *pDword Int seSetPowerSaveModeint PwrSaveMode Int seDrawLineint x1, int y1, int x2, int y2, Dword Color DrawingInt seSetPixellong x, long y, Dword Color Int seGetPixellong x, long y, Dword *pColor Int seGetLutBYTE *pLUT, int Count LUT ManipulationInt seSetLutBYTE *pLut, int Count Int seGetLutEntryint index, Byte *pEntry Int seSetLutEntryint Index, Byte *pEntry Porting Libse to a new target platform Building the HAL library for the target example Building the Libse library for SH3 target example Sample Code Sample code using the S1D13705 HAL API Epson Research and Development Purple Sample code without using the S1D13705 HAL API Pbyte Vancouver Design Center Pclk Vancouver Design Center Epson Research and Development Vancouver Design Center NULL, OPENEXISTING,FILEATTRIBUTENORMAL, Null Vancouver Design Center Bool Header Files Sizeversion Errfailed Function PROTO-TYPES HAL EXE Vancouver Design Center Epson Research and Development This page Left Blank X27A-R-001-03 S1D13705 Register Summary X27A-R-001-03 01/02/13 Document Number X27A-B-001-03 13705CFG Configuration Program This page Left Blank 13705CFG This page Left Blank S1D13705 Supported Evaluation Platforms 13705CFG Usage Installation General Tab 13705CFG Configuration Tabs If your hardware implementation differs from Decode AddressesValues for the Register address and Display Ation platform are examples of possible implementa Display which requires more memory but uses less PowerPreferences Tab For details see the S1D13705 Hardware Functional Specification, document number X27A-A-001-xxClocks Tab Down list or by entering the desired frequency in MHz Actual Clki frequency used for configuration isSource for both Pclk and Mclk Clki frequency must be selected from the drop Panel Tab These settings define the polarity of the Fpline Ically for configuring 8-bit color STN panels8 bit. When an active panel type is selected When the panel type is TFT, Single is automatically Refer to S1D13705 Hardware Functional Specifi Cation, document number X27A-A-001-xx, for a Complete description of the Fpframe pulse settingsPanel manufacturers recommended settings. If the file Settings contained in the file Hardware Power Save function is not available Panel Power TabGPIO0 is enabled. When this box is unchecked, Registers Tab Open 13705CFG Menus Save As Save Configure Multiple Export About 13705CFG Enable TooltipsComments ERD on the Web Document No. X27A-B-002-02 13705SHOW Demonstration Program This page Left Blank 13705SHOW PC platform at the prompt, type Download the program 13705SHOW to the systemUse alternate portrait mode Continuously update display memory Program Messages Error Did not find a 13705 device This page Left Blank Document No. X27A-B-003-02 13705SPLT Display Utility This page Left Blank 13705SPLT Manual mode Move Screen 2 up Move Screen 2 down Enables manual split screen operationEnables automatic split screen operation Timer is used to move screen 13705SPLT Example This page Left Blank Document No. X27A-B-004-02 13705VIRT Display Utility This page Left Blank 13705VIRT Enable alternate portrait mode. Selecting this Defaults to virtual width = = physical width xForce landscape display mode to be set Force portrait display mode to be set Virtual screen shows in the lower left 13705VIRT ExampleVirtual screen shows in the upper right Display Unable to use virtual mode at xx BPP Document No. X27A-B-005-04 13705PLAY Diagnostic Utility This page Left Blank 13705PLAY Writes data to the register specified by the index Writes data to the LUT index when data isDownload the program 13705PLAY to the system Reads/writes the registers 13705PLAY Example Scripting Program Messages This page Left Blank Document No. X27A-B-006-03 13705BMP Demonstration Program This page Left Blank 13705BMP currently views only Windows BMP format images 13705BMPAt the prompt, type Error Did not find an S1D13705 device This error message should never bee seen. Contact ERD Document No. X27A-B-007-03 13705PWR Power Save Utility This page Left Blank 13705PWR Displays this usage message Sets enables hardware power save mode REG03h bitDownload the program 13705PWR to the system Error Did not find a 13705 device This page Left Blank Document Number X27A-E-001-03 Windows CE 2.x Display Drivers X27A-E-001-03 Windows CE 2.x Display Drivers Example Driver Builds With this line Ddi.dll $FLATRELEASEDIR\EPSON.dll Ddi.dll $FLATRELEASEDIR\ddivga2.dll NK SHDdi.dll $FLATRELEASEDIR\ddivga8.dll NK SH Ddi.dll $FLATRELEASEDIR\ddis364.dll Vancouver Design Center If CEPCDDIS1D13705 Find the section shown below, and insert the lines as marked Endif Ddi.dll $FLATRELEASEDIR\ddis364.dll NK SH Epson Research and Development Copy NK.BIN and HIMEM.SYS to c\ Boot the system Installation for Cepc Environment Compile Switches Configuration Mode File Comments This page Left Blank Document Number X27A-E-002-03 Wind River WindML v2.0 Display Drivers X27A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers Building a WindML v2.0 Display Driver If necessary, generate a new mode0.h configuration file Make CPU=PENTIUM ugl This page Left Blank Document Number X27A-E-003-02 Wind River UGL v1.2 Display Drivers X27A-E-003-02 Issue Date 01/02/13 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Document Number X27A-E-004-02 Linux Console Driver X27A-E-004-02 Issue Date 01/09/19 Linux Console Driver Building the Console Driver for Linux Kernel Epson Research and Development Vancouver Design Center To the directory /usr/src/linux/drivers/video/epson Vancouver Design Center Epson Research and Development This page Left Blank Document Number X27A-E-005-01 QNX Photon v2.0 Display Driver This page Left Blank QNX Photon v2.0 Display Driver Build the Driver Configure the DriverBuilding the Photon v2.0 Display Driver Unpack the Graphics Driver Development Kit Archive Run the Driver Installing the Driver Comments Document No. X00A-E-003-04 S1D13XXX 32-Bit Windows Device Driver Installation Guide X00A-E-003-04 Issue Date 01/04/17 Video Controller S1D13xxx Display Type S1D13XXX 32-Bit Windows Device Driver Installation GuideDriver Requirements Windows NT Version All ISA Bus Evaluation Cards WindowsAll PCI Bus Evaluation Cards Windows 98/ME ADD/NEW Hardware Windows 95 OSR2 Previous Versions of Windows All ISA Bus Evaluation Cards Document Number X27A-G-005-03 S5U13705B00C Rev .0 ISA Bus S1D13705 X27A-G-005-03 Issue Date 01/02/13 Parts List Schematic Diagrams Installation and Configuration This page Left Blank S1D13705B00C Schematic Diagram 1 of 4 This page Left Blank Features Host Bus Selection Installation and ConfigurationConfiguration DIP Switch Settings Iovdd Selection Jumper SettingsRD/WR# Signal Selection Pulled up to Iovdd No Connection BS# Signal Selection Pulled up to Iovdd No Connection Even LCD Signal Connector J5 PinoutPins LCD Interface Pin Mapping Comments CPU/Bus Interface Connector PinoutsCPU/BUS Connector H1 Pinout Connector CPU/BUS Connector H2 Pinout DB150 D150 WE1# Host Bus Interface Pin Mapping Embedded Memory Support Technical Description Expanded Memory Manager Support ISA Bus SupportNon-ISA Bus Support Display Adapter Card Support Clock Input Support Decoding Logic Color Passive LCD Panel Support LCD Panel Voltage SettingPower Save Modes Monochrome LCD Panel Support 13 CPU/Bus Interface Header Strips Adjustable LCD Panel Negative Power SupplyAdjustable LCD Panel Positive Power Supply Item # Qty/board Designation Part Value Description Parts List S1D13705B00C Schematic Diagram 1 Schematic Diagrams S1D13705B00C Vancouver Epson Research S1D13705B00C Schematic Diagram 4 This page Left Blank Document Number X27A-G-014-02 S1D13705 X27A-G-014-02 Issue Date 2002/09/16 LCD Interface Pin Mapping Technical Description Introduction Features Installation and ConfigurationParts List Schematics Board Layout Technical Support CPU Interface This page Left Blank Configuration DIP Switch SW1 Location This page Left Blank Introduction Features Configuration DIP Switch SW1 Location Configuration DIP Switches Not Used SW1-6 SH-4SH-3 Big Endian bus interface Little Endian bus interface SW1-5 PCI Bridge Fpga Configuration JumpersJumper Summary Jumper Function Position No Jumper Configuration Jumper JP2 Location Configuration Jumper JP4 Location Configuration Jumper JP6 Location CPU Interface Pin Mapping CPU InterfaceCPU Interface Pin Mapping Connector Comments Pin No CPU Bus Connector Pin MappingCPU Bus Connector H1 Pinout CPU Bus Connector H2 Pinout Dual LCD Signal Connector J52LCDPWR on J5 can be inverted by setting JP6 to S1D13705 Embedded Memory Adjustable LCD Panel Positive Power Supply VddhPCI Bus Support Direct Host Bus Interface Support Passive/Active LCD Panel Support Adjustable LCD Panel Negative Power Supply Vlcd Clock Options Software Document Sources ReferencesDocuments Quantity Reference Part Description Pin DIP socket Machined socket, 8-pin RD-0412 Xentek RD-0412, positive power SupplyEPN001 Xentek EPN001, negative power Supply EPF6016TC144-2 Altera EPF6016TC144-2 S1D13705B00C Schematics 1 Schematics S1D13705B00C Schematics 2 S1D13705B00C Schematics 3 S1D13705B00C Schematics 4 S1D13705B00C Schematics 5 Board Layout Epson LCD Controllers S1D13705 Technical Support Document Number X27A-E-006-01 Windows CE 3.x Display Drivers X27A-E-006-01 Windows CE 3.x Display Drivers Example Driver Builds If CEPCDDIS1D13X0X Ddi.dll $FLATRELEASEDIR\ddiflat.dll NK SH If Cepcddiflat If CEPCDDIS1D13X0X Endif Epson Research and Development Installation for Cepc Environment EnablePreferVmem GrayPalette Resource Management Issues Vancouver Design Center Simple Display Driver Configuration Comments Document Number X27A-G-004-02 Interfacing to the Toshiba Mips TMPR3912 Microprocessor This page Left Blank Software Technical Support Using the ITE IT8368E PC Card BufferDirect Connection to the Toshiba TMPR3912 This page Left Blank S1D13705 to TMPR3912 Direct Connection S1D13705 to TMPR3912 Connection Using an IT8368E This page Left Blank Introduction Interfacing to the TMPR3912 AB151 A151 S1D13705 Host Bus InterfaceHost Bus Pin Connection S1D13705 Generic #1 Generic #2 Pin Names Generic #1 Interface Mode Generic #2 Interface Mode General Description Direct Connection to the Toshiba TMPR3912 Big Endian S1D13705 ConfigurationS1D13705 Configuration for Direct Connection Memory Mapping and Aliasing Hardware Description Using the ITE IT8368E PC Card Buffer S1D13705 to TMPR3912 Connection Using an IT8368E At 128K byte intervals IT8368E Configuration16M byte Card 1 IO 16M byte 32M byte Card 2 Attribute S1D13705 Configuration Using the IT8368E= configuration for connection using ITE IT8368E 16M byte Card 2 IO Software Integrated Technology Express, Inc Toshiba Mips TMPR3912 Processor ITE IT8368EJapan North America Taiwan, R.O.C Europe Hong Kong Singapore This page Left Blank Document Number X27A-G-006-02 S1D13705 Power Consumption S1D13705 Power Consumption X27A-G-006-02 S1D13705 Power Consumption Conditions S1D13705 Total Power Consumption Summary This page Left Blank Document Number X27A-G-007-04 X27A-G-007-04 Issue Date 01/02/13 Interfacing to the MC68VZ328 Introduction Interfacing to the MC68328Interfacing to the MC68EZ328 Technical Support List of Tables This page Left Blank Introduction Chip-Select Module Interfacing to the MC68328MC68328 System Bus WE0# Connect to IO V DD S1D13705 Host Bus InterfaceHost Bus Pin Connection S1D13705 MC68K #1 Generic #1 Pin Names Generic #1 Interface Mode 3 MC68K #1 Interface Mode Hardware Description Using The MC68K #1 Host Bus InterfaceMC68328 To S1D13705 Interface Using The Generic #1 Host Bus Interface Host Bus Interface Selection 2 S1D13705 Hardware Configuration3 MC68328 Chip Select Configuration Summary of Power-On/Reset Options Epson Research and Development MC68EZ328 System Bus Interfacing to the MC68EZ328 S1D13705 Generic #1 Pin Names Generic #1 Interface Mode MC683EZ28 To S1D13705 Interface = configuration for MC68EZ328 support 3 MC68EZ328 Chip Select Configuration Epson Research and Development MC68VZ328 System Bus Interfacing to the MC68VZ328 S1D13705 Host Bus Interface Generic #1 Interface Mode 3 MC68K #1 Interface Mode MC68VZ328 To S1D13705 Interface CSB1 CS# = configuration for MC68VZ328 support 3 MC68VZ328 Chip Select and Pin Configuration Software Motorola Inc. Motorola Literature Distribution Center, 800 Motorola Dragonball Processors Document Number X27A-G-008-02 Interfacing to the NEC VR4102/VR4111 Microprocessor X27A-G-008-02 Issue Date 01/02/13 Epson LCD Controllers S1D13705 NEC Electronics Inc Host Bus Pin Connection Generic #2 Interface ModeIntroduction Interfacing to the NEC VR4102/VR4111 VR4102/VR4111 to S1D13705 Interface This page Left Blank NEC VR4102/VR4111 Read/Write Cycles This page Left Blank Introduction Overview Interfacing to the NEC VR4102/VR4111NEC VR4102/VR4111 System Bus Lcdrdy LCD Memory Access Cycles S1D13705 Generic #2 Pin Names Generic #2 Interface Mode Busclk BS# RD/WR# VR4102/VR4111 to S1D13705 Interface See Host Bus Selection table below S1D13705 Hardware Configuration NEC VR4102/VR4111 Configuration Software References Santa Clara California Tel 800 Fax 800 NEC Electronics IncNEC Electronics Inc. U.S.A This page Left Blank Document Number X27A-G-009-02 Interfacing to the PC Card Bus This page Left Blank PC Card to S1D13705 Interface Memory Access CyclesInterfacing to the PC Card Bus S1D13705 Bus Interface This page Left Blank PC Card Read Cycle This page Left Blank Introduction PC Card Overview Memory Access CyclesInterfacing to the PC Card Bus PC Card System Bus PC Card Read Cycle S1D13705 Bus Interface Generic #2 Interface Mode Hardware Connections PC Card to S1D13705 Interface Register/Memory Mapping Signal Low High Software PC Card Pcmcia Standard March Pcmcia PC Card Standard Document Number X27A-G-010-02 Interfacing to the Motorola MPC821 Microprocessor X27A-G-010-02 Issue Date 01/02/13 MPC821 to S1D13705 Interface Host Bus Interface Modes Generic #1 Host Bus Interface ModeIntroduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction MPC821 Bus Overview Interfacing to the MPC821MPC8xx System Bus Normal Non-Burst Bus Transactions Power PC Memory Read Cycle Burst Cycles Power PC Memory Write Cycle General-Purpose Chip Select Module Gpcm Memory Controller Module User-Programmable Machine UPM Host Bus Interface Modes Generic #1 Host Bus Interface Mode Typical Implementation of MPC821 to S1D13705 Interface MPC821 to S1D13705 Interface List of Connections from MPC821ADS to S1D13705 MPC821ADS Evaluation Board Hardware Connections P12-A5, P12-B5, P12-A6, P12-B6 P6-A14 WE0#P12-A1, P12-B1, P12-A2, P12-B2 P12-A3, P12-B3, P12-A4, P12-B4 Configuration Settings MPC821 Chip Select Configuration 1FFE0 Test Software Epson Research and Development Software Motorola Inc. Literature Distribution Center 800 Motorola MPC821 Processor Epson LCD/CRT Controllers S1D13705 Document Number X27A-G-011-02 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A-G-011-02 Issue Date 01/02/13 Epson LCD Controllers S1D13705 Motorola MCF5307 Processor Host Bus Pin Connection Generic #1 Interface ModeIntroduction Interfacing to the MCF5307 This page Left Blank List of Tables This page Left Blank Introduction MCF5307 System Bus Interfacing to the MCF5307 MCF5307 Memory Read Cycle Chip-Select Module S1D13705 Bus Interface Generic #1 Interface Mode Typical Implementation of MCF5307 to S1D13705 Interface MCF5307 To S1D13705 Interface Little Endian Big Endian = configuration for MFC5307 support MCF5307 Chip Select Configuration Software References Motorola MCF5307 Processor Document Number X27A-G-012-02 Interfacing to the Philips Mips PR31500/PR31700 Processor This page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank S1D13705 to PR31500/PR31700 Direct Connection S1D13705 to PR31500/PR31700 Connection Using an IT8368E This page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13705 Host Bus Interface Generic #1 Interface Mode Generic #2 Interface Mode S1D13705 to PR31500/PR31700 Direct Connection Direct Connection to the Philips PR31500/PR31700 Memory Mapping and Aliasing S1D13705 Configuration and Pin Mapping Using the ITE IT8368E PC Card Buffer S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 S1D13705 aliased 128 times 0900 0000h S1D13705 Configuration Software Philips Semiconductors Philips Mips PR31500/PR31700 Processor Document Number X00A-G-004-02 S5U13704/5 TMPR3912/22U CPU Module S5U13704/5 TMPR3912/22U CPU Module Table of Contents This page Left Blank List of Figures List of Tables This page Left Blank General Description Bus Interface Modes S1D13704/5 Bus Interface Generic #2 Interface Mode Hardware Connections TMPR3912/22U and S1D13704/5 Interface S1D13704/5 Generic #2 Interface Pin Mapping S1D13704/5 Configuration and Pin Mapping= configuration for Toshiba TMPR3912/22U host bus interface Memory Mapping and Aliasing Clki Clock Signals BusclkLCD Connectors 1 50-pin LCD Module Connector, J3 CPU Module Description 3 S1D13704\75 Chip Select Standard Epson LCD Connector, J4LCD Controller 1 S1D13704 vs. S1D13705 Lcdpwr Polarity This page Left Blank Document Number X27A-G-013-02 Interfacing to the NEC VR4181A Microprocessor X27A-G-013-02 VR4181A to S1D13705 Interface NEC VR4181A System Bus Overview LCD Memory Access SignalsIntroduction Interfacing to the NEC VR4181A This page Left Blank Typical Implementation of VR4181A to S1D13705 Interface This page Left Blank Introduction NEC VR4181A System Bus Interfacing to the NEC VR4181A LCD Memory Access Signals BHE# Generic #2 Interface Mode Typical Implementation of VR4181A to S1D13705 Interface VR4181A to S1D13705 Interface S1D13705 Hardware Configuration NEC VR4181A Configuration Software References Technical Support This page Left Blank Document Number X27A-G-015-01 Interfacing to an 8-bit Processor X27A-G-015-01 Issue Date 01/12/20 Epson LCD/CRT Controllers S1D13705 Interfacing to an 8-bit ProcessorGeneric 8-bit Processor System Bus Bit Processor to S1D13705 Interface This page Left Blank List of Tables This page Left Blank Introduction Generic 8-bit Processor System Bus Interfacing to an 8-bit Processor S1D13705 Generic #2 Description Pin Names Generic #2 Interface Mode Bit Processor to S1D13705 Interface Little Endian Big Endian = required configuration for this application Software References Technical Support This page Left Blank