Epson S1D13705 technical manual Generic #1 Interface Timing, Generic #1 Timing

Page 32 Epson Research and Development

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7.1.5 Generic #1 Interface Timing

	TBCLK
BCLK
A[16:0]		VALID
CS#
	t1			t2
WE0#,WE1#
RD0#, RD1#
	t3			t5
D[15:0]	Hi-Z	VALID
(write)
	t4	t6		t7
D[15:0]	Hi-Z		VALID	Hi-Z
(read)
	t8	t9		t10
WAIT#	Hi-Z			Hi-Z
			t11
		Figure 7-5: Generic #1 Timing

Table 7-5: Generic #1 Timing

Symbol	Parameter	Min	Max	Units
fBCLK	Bus Clock frequency		50	MHz
TBCLK	Bus Clock period	1/fBCLK		MHz
t1	A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1#	0		ns
	low (read cycle)
t2	WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to	0		ns
	A[16:0], CS# invalid
t3	WE0#, WE1# low to D[15:0] valid (write cycle)		TBCLK
t4	RD0#, RD1# low to D[15:0] driven (read cycle)		17	ns
t5	WE0#, WE1# high to D[15:0] invalid (write cycle)	0		ns
t6	D[15:0] valid to WAIT# high (read cycle)	0		ns
t7	RD0#, RD1# high to D[15:0] high impedance (read cycle)		10	ns
t8	WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to		16	ns
	WAIT# driven low
t9	BCLK to WAIT# high		16	ns
t10	WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to		16	ns
	WAIT# high impedance
t11	WAIT# high to WE0#, WE1#, RD0#, RD1# high	1TBCLK

Note

BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 84

S1D13705	Hardware Functional Specification
X27A-A-001-10	Issue Date: 02/02/01