Epson S1D13705 technical manual LCD Memory Access Cycles, Lcdrdy

Epson Research and Development Page 9

Vancouver Design Center

2.1.2 LCD Memory Access Cycles

Once an address in the LCD block of memory is placed on the external address bus, ADD[25:0], the LCD chip select, LCDCS#, is driven low. The read or write enable signals, RD# and WR#, are driven low for the appropriate cycle. LCDRDY is driven low by the S1D13705 to insert wait states into the cycle. The high byte enable is driven low for 16-bit transfers and high for 8-bit transfers.

Figure 2-1: “NEC VR4102/VR4111 Read/Write Cycles,” on page 9 shows the read and write cycles to the LCD Controller Interface.

TCLK
ADD[25:0]	VALID
SHB#
LCDCS#
WR#,RD#
D[15:0]	VALID
(write)
D[15:0]	Hi-Z	VALID	Hi-Z
(read)
LCDRDY
	Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles

Interfacing to the NEC VR4102/VR4111 Microprocessor	S1D13705
Issue Date: 01/02/13	X27A-G-008-02