Epson S1D13705 7.1.3 Motorola MC68K #1 Interface Timing

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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.1.3 Motorola MC68K #1 Interface Timing
Figure 7-3: MC68K #1 Bus Timing (MC68000)
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
Table 7-3: MC68K #1 Bus Timing (MC68000)
Symbol Parameter Min Max Units
fCLK Bus Clock Frequency 33 MHz
TCLK Bus Clock period 1/fCLK
t1 A[16:1], CS# valid before AS# falling edge 0 ns
t2 A[16:1], CS# hold from AS# rising edge 0 ns
t3 AS# low to DTACK# driven high 16 ns
t4 CLK to DTACK# low 15 ns
t5 CLK to AS#, UDS#, LDS# high 1TCLK
t6 AS# high to DTACK# high 20 ns
t7 AS# high to DTACK# high impedance TCLK
t8 UDS#, LDS# falling edge to D[15:0] valid (write cycle) TCLK
t9 D[15:0] hold from AS# rising edge (write cycle) 0 ns
t10 UDS#, LDS# falling edge to D[15:0] driven (read cycle) 15 ns
t11 D[15:0] valid to DTACK# falling edge (read cycle) 0 ns
t12 UDS#, LDS# rising edge to D[15:0] high impedance 10 ns
t3
A[16:1]
AS#
UDS#, LDS#
VALID
VALID
t1
t9
t2
t8
R/W#
Hi-Z Hi-Z
INVALID
t6
t4
DTACK# Hi-Z
Hi-Z
CLK
t7
TCLK
CS#
t10 t11
Hi-Z VALID Hi-Z
D[15:0]
D[15:0]
t12
(write
(read)
t5