Page 30

Epson Research and Development

Vancouver Design Center

7.1.3 Motorola MC68K #1 Interface Timing

 

TCLK

 

 

CLK

 

 

 

A[16:1]

 

VALID

 

CS#

 

 

R/W#

 

 

 

 

t1

 

t2

AS#

 

 

 

UDS#, LDS#

INVALID

 

 

 

 

t5

t7

 

t3

t4

 

 

 

 

 

t6

DTACK#

Hi-Z

 

Hi-Z

 

 

 

 

 

t8

t9

D[15:0]

Hi-Z

Hi-Z

 

(write

VALID

 

 

 

t10

t11

t12

D[15:0]

Hi-Z

 

Hi-Z

(read)

VALID

 

 

 

Figure 7-3: MC68K #1 Bus Timing (MC68000)

 

Table 7-3: MC68K #1 Bus Timing (MC68000)

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

fCLK

Bus Clock Frequency

 

33

MHz

TCLK

Bus Clock period

1/fCLK

 

 

t1

A[16:1], CS# valid before AS# falling edge

0

 

ns

 

 

 

 

 

t2

A[16:1], CS# hold from AS# rising edge

0

 

ns

 

 

 

 

 

t3

AS# low to DTACK# driven high

 

16

ns

 

 

 

 

 

t4

CLK to DTACK# low

 

15

ns

 

 

 

 

 

t5

CLK to AS#, UDS#, LDS# high

1TCLK

 

 

t6

AS# high to DTACK# high

 

20

ns

 

 

 

 

 

t7

AS# high to DTACK# high impedance

 

TCLK

 

t8

UDS#, LDS# falling edge to D[15:0] valid (write cycle)

 

TCLK

 

t9

D[15:0] hold from AS# rising edge (write cycle)

0

 

ns

 

 

 

 

 

t10

UDS#, LDS# falling edge to D[15:0] driven (read cycle)

 

15

ns

 

 

 

 

 

t11

D[15:0] valid to DTACK# falling edge (read cycle)

0

 

ns

 

 

 

 

 

t12

UDS#, LDS# rising edge to D[15:0] high impedance

 

10

ns

 

 

 

 

 

Note

CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off

BCLK Between Accesses” on page 84

S1D13705

Hardware Functional Specification

X27A-A-001-10

Issue Date: 02/02/01

Page 36
Image 36
Epson S1D13705 Motorola MC68K #1 Interface Timing, AS# high to DTACK# high AS# high to DTACK# high impedance