S1D13705B00C Schematics 1 | Epson specs

X27A-G-014	S1D13705
-02

S5U13705B00C Rev. 2.0 Evaluation Board User Manual Issue Date: 2002/09/16

Figure 10-1: S1D13705B00C Schematics (1 of 5)

D

C

B

A

5

4

3

2

1

4,5

AB[16:0]

AB[16:0]

U1

IOVDD

R1

AB0

70

AB0

R2

R3

R4

R5

R6

AB1

69

15K

15K

15K

15K

15K

15K

AB1

AB2

68

AB2

AB3

67

AB3

AB4

66

SW1

AB5

65

AB4

1

12

CNF0

AB5

AB6

64

AB6

2

11

CNF1

AB7

63

3

10

CNF2

AB8

62

AB7

4

9

CNF3

AB9

59

AB8

5

8

R7

0R

CNF4

AB10

58

AB9

6

7

SUSPEND

CNF4

3

AB11

57

AB10

AB11

Not Populated

AB12

56

AB12

SW DIP-6

AB13

55

AB13

AB14

54

AB14

AB15

53

AB15

AB16

45

AB16

R8

0R

CNF4

LCDPWR

43

LCDPWR

2,3

R9

4,5

DB[15:0]

DB[15:0]

0R

Not Populated

FPFRAME

39

FPFRAME

2

DB0

FPLINE

38

FPLINE

2

19

DB0

28

FPSHIFT

FPSHIFT

2

DB1

18

42

DB1

DRDY

DRDY

2

DB2

17

DB2

DB3

16

DB3

DB4

15

DB4

FPDAT[7:0]

DB5

14

FPDAT[7:0]

2

DB5

DB6

13

DB7

12

DB6

FPDAT0

37

FPDAT0

DB7

DB8

11

36

FPDAT1

DB8

FPDAT1

DB9

9

35

FPDAT2

DB9

FPDAT2

DB10

8

34

FPDAT3

DB10

FPDAT3

DB11

7

33

FPDAT4

DB11

FPDAT4

DB12

6

32

FPDAT5

DB12

FPDAT5

DB13

5

31

FPDAT6

DB13

FPDAT6

IOVDD

DB14

4

DB14

FPDAT7

30

FPDAT7

+5V

14

VCC

NC

1

14

U8A

DB15

3

DB15

C25

7

GND

OUT

8

1

2

BUSCLK

5

7

79

0.1uF

U7

50MHz

4,5

RD/WR#

78

RD/WR#

4,5

WE1#

WE1#

74AHC04/SO

4,5

WE0#

77

WE0#

4,5

RD#

76

RD#

FPDAT8/GPIO1

26

FPDAT8

2

BS#

75

25

4,5

BS#

BS#

FPDAT9GPIO2

FPDAT9

2

24

JP2

FPDAT10/GPIO3

FPDAT10

2

4,5

RESET#

73

RESET#

23

FPDAT11/GPIO4

FPDAT11

2

1

4,5

CS#

74

2

CS#

3

JP7

HEADER 3

71

BCLK

CNF0

4

BCLK

3

CNF0

49

2

51

CLKI

CNF1

48

CNF1

47

CNF2

IOVDD

1

CNF2

4,5

WAIT#

2

WAIT#

CNF3

46

CNF3

IOVDD

HEADER 3

+5V

14

VCC

NC

1

14

U8B

44

TESTEN

C17

C24

7

GND

OUT

8

3

4

0.1uF

7

0.1uF

U2

6MHz

74AHC04/SO

By-pass Capacitors (1 per power pin)

GPIO0

22

SUSPEND

U8C

IOVDD

3.3V

1

COREVDD

14

14

U8F

C1

C2

C3

C4

21

COREVDD

5

6

13

12

41

7

7

0.1uF

0.1uF

0.1uF

0.1uF

COREVDD

61

COREVDD

IOVDD

10

IOVDD

74AHC04/SO

74AHC04/SO

C5

C6

C7

29

IOVDD

52

0.1uF

0.1uF

0.1uF

IOVDD

IOVDD

IOVDD

IOVDD

14

U8D

14

U8E

R10

20

VSS

9

8

11

10

27

VSS

7

7

40

15K

VSS

JP3

50

VSS

74AHC04/SO

74AHC04/SO

60

VSS

3

BS#

72

VSS

JP1

80

2

VSS

1

R11

1

3.3V

HEADER 3

2

IOVDD

SED1375F0A

3

+5V

15K

HEADER 3

Title

S5U13705B00C - PCI bus: 13705F0A Chip

Size

Document Number

Rev

<Doc>

2.0

Date:

Tuesday, October 02, 2001

Sheet

1

of

5

5

4

3

2

1

D

C

B

A

10 Schematics

Page 26

Vancouver	Epson Research and
Design Center	Development

Image 338

Epson technical manual S1D13705B00C Schematics 1

Contents

S1D13705 Document No. X27A-Q-001-04 This page Left Blank Customer Support Information This page Left Blank S1D13705 Embedded Memory LCD Controller February Software Suspend mode LCD power-down sequencing Embedded 80K byte Sram display buffer Hardware Functional Specification Document Number X27A-A-001-10 This page Left Blank Table of Contents SwivelView Power Save ModesRegisters Mechanical Data List of Tables This page Left Blank List of Figures 2 Bit-per-pixel Monochrome Mode Data Output Path Overview Description IntroductionScope CPU Interface FeaturesIntegrated Frame Buffer Display Support Miscellaneous Display ModesClock Source Package Typical System Implementation Diagrams Typical System Diagram SH-4 Bus Typical System Diagram M68K #1 Bus Typical System Diagram Generic #1 Bus Host Interface Functional Block DiagramFunctional Block Descriptions Memory Controller Look-Up Table Power SavePower Save contains the power save mode circuitry LCD Interface Package type 80 pin surface mount QFP14 PinsPinout Diagram Pin Names Type Pin # Cell Pin DescriptionKey Description For MC68K #1, this pin inputs the R/W# signal For SH-3/SH-4 mode, this pin inputs the write enable signalInput This pin inputs the chip select signal For the lower data byte WE0# Pin Name Type Pin # Cell Miscellaneous Power SupplyClock Input Pin Name Type Pin # Driver Description Host Bus Interface Pin Mapping Summary of Configuration OptionsSummary of Power On/Reset Options Host Bus Interface Pin Mapping Bit Pin Name Bit Dual Single 12-bit Format LCD Interface Pin MappingLCD Interface Pin Mapping Absolute Maximum Ratings C. CharacteristicsInput Specifications Recommended Operating Conditions for Core VDD = 3.3V ± 10% Output Specifications Bus Interface Timing 1 SH-4 Interface Timing Bus Clock period Symbol Parameter Min Max UnitsBus Clock frequency MHz T11 Rising edge CSn# to RDY# high impedance T14 T15 D150 2 SH-3 Interface TimingT12 T13 Write T16 T17 D150 Symbol Parameter Min Maxa Units UDS#, LDS# falling edge to D150 valid write cycle Motorola MC68K #1 Interface TimingAS# high to DTACK# high AS# high to DTACK# high impedance DS# falling edge to D3116 valid write cycle Motorola MC68K #2 Interface TimingAS# high to DSACK1# high AS# high to DSACK1# high impedance AS#, DS# rising edge to D3116 high impedance Generic #1 Interface Timing Generic #1 Timing Generic #2 Interface Timing Generic #2 Timing Input Clock period Clki Clock Input RequirementsInput Clock Frequency Clki MHz Input Clock Pulse Width High Clki Input Clock Pulse Width High Bclk Input Clock Frequency Bclk MHzInput Clock period Bclk Display Interface Power On/Reset TimingSymbol Parameter Min Typ Max Units REG03h to FPLINE, FPFRAME, FPSHIFT, FPDAT, Drdy REG03h bits FP Signals Active Inactive Power Down/Up TimingLcdpwr Override REG03h bit HW Power Save Active Inactive Single Monochrome 4-Bit Panel Timing 11 Single Monochrome 4-Bit Panel Timing Sync Timing Data Timing Single Monochrome 8-Bit Panel Timing 13 Single Monochrome 8-Bit Panel Timing = REG08h bits 4-0 x 8 + 4Ts Single Color 4-Bit Panel Timing 15 Single Color 4-Bit Panel Timing = REG08h bits 4-0 x 8 + 1.5Ts Single Color 8-Bit Panel Timing Format 17 Single Color 8-Bit Panel Timing Format T6a T6b T7a T14 T11 19 Single Color 8-Bit Panel Timing Format = REG08h bits 4-0 x 8 + 1Ts Dual Monochrome 8-Bit Panel Timing 21 Dual Monochrome 8-Bit Panel Timing = REG04h bits 6-0+1 x 8 + REG08h bits 4-0 + 4 x 8 x 2Ts Dual Color 8-Bit Panel Timing 23 Dual Color 8-Bit Panel Timing = REG08h bits 4-0 x 2x 8 + 17Ts 10 9/12-Bit TFT/D-TFD Panel Timing 25 12-Bit TFT/D-TFD Panel Timing 26 TFT/D-TFD A.C. Timing 18 TFT/D-TFD A.C. Timing Register Descriptions RegistersRegister Mapping Bit Color/Mono Dual/Single Data Width Bit Function Active highPanel Data Format Don’t care High Performance Selection Gray Scale/Color Mode SelectionColor/Mono Bit-Per-Pixel Bit Display Mode High Performance BPP Bit Display Modes Video data is inverted after the Look-Up Table Video Mode Select Options belowInverse Video Mode Select Options Hardware Power Save/GPIO0 Operation Software Power Save Mode Selection Size Bit This register must not be set to a value less than 03hVertical Panel Following constraint must be satisfied Fpline Start Vertical Non MOD Rate Bit Screen 1 Start Screen 2 Start Vertical Size Bit MemoryOffset Bit Screen-Register Relationship, Split Screen LUT Address REG18h Gpio Configuration Control Register LUT Data Bit Selection of SwivelView Mode SwivelView Mode Enable Mode Select Pixel Clock Pclk Select Mode Enable Mode Select Selection of Pclk and Mclk in SwivelView ModeCreate a virtual image in SwivelView mode Where CLK is Clki REG02h bit 4 = 0 or CLKI/2 REG02h bit 4 = TFT/D-TFD and Passive Single-Panel modes Passive Dual-Panel modeFrame Rate Calculation Display Data Formats 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Monochrome Modes Bit-per-pixel Monochrome modeLook-Up Table Architecture Green Look-Up Table LUT is used for all monochrome modes 4 Bit-per-pixel Monochrome Mode Data Output Path Bit-per-pixel Color Mode Color Modes 2 Bit-per-pixel Color Mode Data Output Path 4 Bit-per-pixel Color Mode Data Output Path 8 Bit-per-pixel Color Mode Data Output Path Default SwivelView Mode SwivelView Where bpb is bits-per-byte and bpp is bits-per-pixel How to Set Up Default SwivelView ModeWhere bpp is bits-per-pixel and bpb is bits-per-byte Alternate SwivelView Mode Start Address 480 Image refreshed by S1D13705 How to Set Up Alternate SwivelView Mode Default and Alternate SwivelView Mode Comparison Comparison Between Default and Alternate SwivelView ModesSwivelView Mode Limitations Default SwivelView Mode Alternate SwivelView Mode Hardware Power Save Mode Power Save ModesSoftware Power Save Mode Power Save Mode Function Summary Power Save Mode Function SummaryPanel Power Up/Down Sequence Hardware Software Normal Turning Off Bclk Between Accesses Software Power Save Clock Requirements S1D13705 Internal Clock Requirements 14.0 ± 12.0 ± Index Mechanical DataQFP14 80 pin Unit mm 125 Sales and Technical Support Japan North America Taiwan This page Left Blank Programming Notes and Examples Document Number X27A-G-002-03 This page Left Blank Memory Models LCD Power Sequencing and Power Save ModesIntroduction Initialization Look-Up Table LUT Identifying the S1D13705 Hardware Abstraction Layer HAL Sample Code S1D13705 Initialization Sequence This page Left Blank Introduction Register Values InitializationDisplay Buffer Location Register Value hex See Also Frame Rate CalculationS1D13705 Initialization Sequence = Horizontal Display Period in pixels Where Pclk = Pixel clock in HzFor a dual passive panel the formula is = Horizontal Non-Display Period in pixels Epson Research and Development Bit Pixel Memory Models1 Bit-Per-Pixel 2 Colors/Gray Shades Pixel Bit 2 Bit-Per-Pixel 4 Colors/Gray Shades4 Bit-Per-Pixel 16 Colors/Gray Shades Eight Bit-Per-Pixel 256 Colors Green bit Look-Up Table LUT Look-Up Table Registers LUT Data Index Red Green Blue Look-Up Table OrganizationColor Modes Unused entries Example LUT Values for 2 Bpp Color Mode Indicates unused entries Bpp color Index Index Address Red Green Blue Gray Shade ModesRecommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade Suggested LUT Values for 4 Bpp Gray Shade Advanced Techniques Virtual Display REG11h Memory Address Offset Register RegistersExamples Offset Panning and Scrolling REG0Dh Screen 1 Display Start Address 1 MSB Number of Pixels Panned Using Start AddressREG0Ch Screen 1 Display Start Address 0 LSB REG10h Screen 1 Display Start Address 2 MSB Panning to the left To scroll down Split Screen 320x240 Single Panel For Split Screen REG12 Screen 1 Vertical Size LSB REG13 Screen 1 Vertical Size MSB REG0Eh Screen 2 Display Start Address 0 LSB REG0Fh Screen 2 Display Start Address 1 MSB Examples REG03h Mode Register LCD Power Sequencing and Power Save ModesLCD Power Sequencing Hardware Software Power Save Override Enable Bit LCD Enable/Disable Introduction To Hardware Rotation Default Portrait ModeHardware Rotation Portrait Alternate Portrait Mode REG0Dh Screen 1 Start Word Address MSB REG1Bh Portrait Mode RegisterREG0Ch Screen 1 Start Word Address LSB REG0Eh Screen 1 Start Word Address MSB Epson Research and Development Power of 2. In most cases, a virtual Default and Alternate Portrait Mode ComparisonDefault Portrait Mode Alternate Portrait Mode Limitations Examples Vancouver Design Center 16 , 000 FrameRate Vancouver Design Center Identifying the S1D13705 Introduction Contents of the HalstructHardware Abstraction Layer HAL Function Description Using the HAL libraryAPI for 13705HAL Register / Memory Access SeSetInit InitializationInt seRegisterDeviceconst Lphalstruc lpHalInfo General HAL Support Int seGetIdint * pId Int seGetBytesPerScanlineint * pBytes Int seSetBitsPerPixelint BitsPerPixelInt seGetBitsPerPixelint * pBitsPerPixel Int seGetLastUsableBytelong * plLastByte Int seDelayint MilliSecondsInt seGetScreenSizeint * Width, int * Height Int seSetPortraitMethod int Style Advanced HAL FunctionsInt seSetHighPerformanceBOOL OnOff Int seSetHWRotateint Rotate Int seSplitInitWORD Scrn1Addr, Word Scrn2Addr Int seSplitScreenint Screen, int VisibleScanlines SeVirtInit must be been called before calling seVirtMove Int seVirtInitDWORD VirtX, Dword * VirtYInt seVirtMoveint Screen, int x, int y Int seSetRegint Index, Byte Value Register / Memory AccessInt seGetRegint Index, Byte * pValue Int seReadDisplayByteDWORD Offset, Byte *pByte Int seReadDisplayDwordDWORD Offset, Dword *pDword Int seWriteDisplayBytesDWORD Offset, Byte Value, Dword Count Int seSetPowerSaveModeint PwrSaveMode Int seGetPixellong x, long y, Dword *pColor DrawingInt seSetPixellong x, long y, Dword Color Int seDrawLineint x1, int y1, int x2, int y2, Dword Color Int seGetLutBYTE *pLUT, int Count LUT ManipulationInt seSetLutBYTE *pLut, int Count Int seSetLutEntryint Index, Byte *pEntry Int seGetLutEntryint index, Byte *pEntry Porting Libse to a new target platform Building the Libse library for SH3 target example Building the HAL library for the target example Sample code using the S1D13705 HAL API Sample Code Epson Research and Development Sample code without using the S1D13705 HAL API Purple Pbyte Vancouver Design Center Pclk Vancouver Design Center Epson Research and Development Vancouver Design Center NULL, OPENEXISTING,FILEATTRIBUTENORMAL, Null Vancouver Design Center Header Files Bool Sizeversion Errfailed Function PROTO-TYPES HAL EXE Vancouver Design Center Epson Research and Development This page Left Blank X27A-R-001-03 S1D13705 Register Summary X27A-R-001-03 01/02/13 13705CFG Configuration Program Document Number X27A-B-001-03 This page Left Blank 13705CFG This page Left Blank 13705CFG S1D13705 Supported Evaluation Platforms Installation Usage 13705CFG Configuration Tabs General Tab Ation platform are examples of possible implementa Decode AddressesValues for the Register address and Display If your hardware implementation differs from Display which requires more memory but uses less PowerPreferences Tab For details see the S1D13705 Hardware Functional Specification, document number X27A-A-001-xxClocks Tab Clki frequency must be selected from the drop Actual Clki frequency used for configuration isSource for both Pclk and Mclk Down list or by entering the desired frequency in MHz Panel Tab When the panel type is TFT, Single is automatically Ically for configuring 8-bit color STN panels8 bit. When an active panel type is selected These settings define the polarity of the Fpline Refer to S1D13705 Hardware Functional Specifi Settings contained in the file Complete description of the Fpframe pulse settingsPanel manufacturers recommended settings. If the file Cation, document number X27A-A-001-xx, for a Hardware Power Save function is not available Panel Power TabGPIO0 is enabled. When this box is unchecked, Registers Tab 13705CFG Menus Open Save Save As Configure Multiple Export ERD on the Web Enable TooltipsComments About 13705CFG 13705SHOW Demonstration Program Document No. X27A-B-002-02 This page Left Blank 13705SHOW Continuously update display memory Download the program 13705SHOW to the systemUse alternate portrait mode PC platform at the prompt, type Error Did not find a 13705 device Program Messages This page Left Blank 13705SPLT Display Utility Document No. X27A-B-003-02 This page Left Blank 13705SPLT Timer is used to move screen Enables manual split screen operationEnables automatic split screen operation Manual mode Move Screen 2 up Move Screen 2 down 13705SPLT Example This page Left Blank 13705VIRT Display Utility Document No. X27A-B-004-02 This page Left Blank 13705VIRT Force portrait display mode to be set Defaults to virtual width = = physical width xForce landscape display mode to be set Enable alternate portrait mode. Selecting this Display 13705VIRT ExampleVirtual screen shows in the upper right Virtual screen shows in the lower left Unable to use virtual mode at xx BPP 13705PLAY Diagnostic Utility Document No. X27A-B-005-04 This page Left Blank 13705PLAY Reads/writes the registers Writes data to the LUT index when data isDownload the program 13705PLAY to the system Writes data to the register specified by the index 13705PLAY Example Scripting Program Messages This page Left Blank 13705BMP Demonstration Program Document No. X27A-B-006-03 This page Left Blank 13705BMP currently views only Windows BMP format images 13705BMPAt the prompt, type This error message should never bee seen. Contact ERD Error Did not find an S1D13705 device 13705PWR Power Save Utility Document No. X27A-B-007-03 This page Left Blank 13705PWR Displays this usage message Sets enables hardware power save mode REG03h bitDownload the program 13705PWR to the system Error Did not find a 13705 device This page Left Blank Windows CE 2.x Display Drivers Document Number X27A-E-001-03 X27A-E-001-03 Windows CE 2.x Display Drivers Example Driver Builds Ddi.dll $FLATRELEASEDIR\ddis364.dll Ddi.dll $FLATRELEASEDIR\ddivga2.dll NK SHDdi.dll $FLATRELEASEDIR\ddivga8.dll NK SH With this line Ddi.dll $FLATRELEASEDIR\EPSON.dll Vancouver Design Center Find the section shown below, and insert the lines as marked If CEPCDDIS1D13705 Ddi.dll $FLATRELEASEDIR\ddis364.dll NK SH Endif Epson Research and Development Installation for Cepc Environment Copy NK.BIN and HIMEM.SYS to c\ Boot the system Configuration Compile Switches Mode File Comments This page Left Blank Wind River WindML v2.0 Display Drivers Document Number X27A-E-002-03 X27A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers If necessary, generate a new mode0.h configuration file Building a WindML v2.0 Display Driver Make CPU=PENTIUM ugl This page Left Blank Wind River UGL v1.2 Display Drivers Document Number X27A-E-003-02 X27A-E-003-02 Issue Date 01/02/13 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Linux Console Driver Document Number X27A-E-004-02 X27A-E-004-02 Issue Date 01/09/19 Linux Console Driver Building the Console Driver for Linux Kernel Epson Research and Development Vancouver Design Center To the directory /usr/src/linux/drivers/video/epson Vancouver Design Center Epson Research and Development This page Left Blank QNX Photon v2.0 Display Driver Document Number X27A-E-005-01 This page Left Blank QNX Photon v2.0 Display Driver Unpack the Graphics Driver Development Kit Archive Configure the DriverBuilding the Photon v2.0 Display Driver Build the Driver Installing the Driver Run the Driver Comments S1D13XXX 32-Bit Windows Device Driver Installation Guide Document No. X00A-E-003-04 X00A-E-003-04 Issue Date 01/04/17 Windows NT Version S1D13XXX 32-Bit Windows Device Driver Installation GuideDriver Requirements Video Controller S1D13xxx Display Type All ISA Bus Evaluation Cards WindowsAll PCI Bus Evaluation Cards Windows 98/ME Windows 95 OSR2 ADD/NEW Hardware Previous Versions of Windows All ISA Bus Evaluation Cards S5U13705B00C Rev .0 ISA Bus Document Number X27A-G-005-03 S1D13705 X27A-G-005-03 Issue Date 01/02/13 Installation and Configuration Parts List Schematic Diagrams This page Left Blank S1D13705B00C Schematic Diagram 1 of 4 This page Left Blank Features Host Bus Selection Installation and ConfigurationConfiguration DIP Switch Settings BS# Signal Selection Pulled up to Iovdd No Connection Jumper SettingsRD/WR# Signal Selection Pulled up to Iovdd No Connection Iovdd Selection LCD Interface Pin Mapping LCD Signal Connector J5 PinoutPins Even Connector CPU/Bus Interface Connector PinoutsCPU/BUS Connector H1 Pinout Comments CPU/BUS Connector H2 Pinout Host Bus Interface Pin Mapping DB150 D150 WE1# Technical Description Embedded Memory Support Display Adapter Card Support ISA Bus SupportNon-ISA Bus Support Expanded Memory Manager Support Decoding Logic Clock Input Support Monochrome LCD Panel Support LCD Panel Voltage SettingPower Save Modes Color Passive LCD Panel Support 13 CPU/Bus Interface Header Strips Adjustable LCD Panel Negative Power SupplyAdjustable LCD Panel Positive Power Supply Parts List Item # Qty/board Designation Part Value Description Schematic Diagrams S1D13705B00C Schematic Diagram 1 S1D13705B00C Vancouver Epson Research S1D13705B00C Schematic Diagram 4 This page Left Blank Document Number X27A-G-014-02 S1D13705 X27A-G-014-02 Issue Date 2002/09/16 CPU Interface Introduction Features Installation and ConfigurationParts List Schematics Board Layout Technical Support LCD Interface Pin Mapping Technical Description This page Left Blank Configuration DIP Switch SW1 Location This page Left Blank Introduction Features Configuration DIP Switches Configuration DIP Switch SW1 Location Big Endian bus interface Little Endian bus interface SW1-5 SH-4SH-3 Not Used SW1-6 Jumper Function Position No Jumper Configuration JumpersJumper Summary PCI Bridge Fpga Configuration Jumper JP2 Location Configuration Jumper JP4 Location Configuration Jumper JP6 Location CPU Interface Pin Mapping CPU InterfaceCPU Interface Pin Mapping Connector Comments Pin No CPU Bus Connector Pin MappingCPU Bus Connector H1 Pinout CPU Bus Connector H2 Pinout Dual LCD Signal Connector J52LCDPWR on J5 can be inverted by setting JP6 to Direct Host Bus Interface Support Adjustable LCD Panel Positive Power Supply VddhPCI Bus Support S1D13705 Embedded Memory Adjustable LCD Panel Negative Power Supply Vlcd Passive/Active LCD Panel Support Clock Options Software Document Sources ReferencesDocuments Quantity Reference Part Description EPF6016TC144-2 Altera EPF6016TC144-2 RD-0412 Xentek RD-0412, positive power SupplyEPN001 Xentek EPN001, negative power Supply Pin DIP socket Machined socket, 8-pin Schematics S1D13705B00C Schematics 1 Schematics 2 S1D13705B00C S1D13705B00C Schematics 3 S1D13705B00C Schematics 4 S1D13705B00C Schematics 5 Board Layout Technical Support Epson LCD Controllers S1D13705 Windows CE 3.x Display Drivers Document Number X27A-E-006-01 X27A-E-006-01 Windows CE 3.x Display Drivers Example Driver Builds If CEPCDDIS1D13X0X Ddi.dll $FLATRELEASEDIR\ddiflat.dll NK SH If Cepcddiflat If CEPCDDIS1D13X0X Endif Epson Research and Development Installation for Cepc Environment EnablePreferVmem GrayPalette Resource Management Issues Vancouver Design Center Simple Display Driver Configuration Comments Interfacing to the Toshiba Mips TMPR3912 Microprocessor Document Number X27A-G-004-02 This page Left Blank Software Technical Support Using the ITE IT8368E PC Card BufferDirect Connection to the Toshiba TMPR3912 This page Left Blank S1D13705 to TMPR3912 Connection Using an IT8368E S1D13705 to TMPR3912 Direct Connection This page Left Blank Introduction Interfacing to the TMPR3912 S1D13705 Generic #1 Generic #2 Pin Names S1D13705 Host Bus InterfaceHost Bus Pin Connection AB151 A151 Generic #1 Interface Mode Generic #2 Interface Mode Direct Connection to the Toshiba TMPR3912 General Description Memory Mapping and Aliasing S1D13705 ConfigurationS1D13705 Configuration for Direct Connection Big Endian Using the ITE IT8368E PC Card Buffer Hardware Description S1D13705 to TMPR3912 Connection Using an IT8368E 16M byte IT8368E Configuration16M byte Card 1 IO At 128K byte intervals 16M byte Card 2 IO S1D13705 Configuration Using the IT8368E= configuration for connection using ITE IT8368E 32M byte Card 2 Attribute Software Europe Hong Kong Singapore Toshiba Mips TMPR3912 Processor ITE IT8368EJapan North America Taiwan, R.O.C Integrated Technology Express, Inc This page Left Blank S1D13705 Power Consumption Document Number X27A-G-006-02 S1D13705 Power Consumption X27A-G-006-02 S1D13705 Power Consumption S1D13705 Total Power Consumption Conditions Summary This page Left Blank Document Number X27A-G-007-04 X27A-G-007-04 Issue Date 01/02/13 Interfacing to the MC68VZ328 Introduction Interfacing to the MC68328Interfacing to the MC68EZ328 Technical Support List of Tables This page Left Blank Introduction Chip-Select Module Interfacing to the MC68328MC68328 System Bus S1D13705 MC68K #1 Generic #1 Pin Names S1D13705 Host Bus InterfaceHost Bus Pin Connection WE0# Connect to IO V DD Generic #1 Interface Mode 3 MC68K #1 Interface Mode Hardware Description Using The MC68K #1 Host Bus InterfaceMC68328 To S1D13705 Interface Using The Generic #1 Host Bus Interface Summary of Power-On/Reset Options 2 S1D13705 Hardware Configuration3 MC68328 Chip Select Configuration Host Bus Interface Selection Epson Research and Development Interfacing to the MC68EZ328 MC68EZ328 System Bus S1D13705 Generic #1 Pin Names Generic #1 Interface Mode MC683EZ28 To S1D13705 Interface 3 MC68EZ328 Chip Select Configuration = configuration for MC68EZ328 support Epson Research and Development Interfacing to the MC68VZ328 MC68VZ328 System Bus S1D13705 Host Bus Interface Generic #1 Interface Mode 3 MC68K #1 Interface Mode MC68VZ328 To S1D13705 Interface CSB1 CS# = configuration for MC68VZ328 support 3 MC68VZ328 Chip Select and Pin Configuration Software Motorola Inc. Motorola Literature Distribution Center, 800 Motorola Dragonball Processors Interfacing to the NEC VR4102/VR4111 Microprocessor Document Number X27A-G-008-02 X27A-G-008-02 Issue Date 01/02/13 VR4102/VR4111 to S1D13705 Interface Host Bus Pin Connection Generic #2 Interface ModeIntroduction Interfacing to the NEC VR4102/VR4111 Epson LCD Controllers S1D13705 NEC Electronics Inc This page Left Blank NEC VR4102/VR4111 Read/Write Cycles This page Left Blank Introduction Overview Interfacing to the NEC VR4102/VR4111NEC VR4102/VR4111 System Bus LCD Memory Access Cycles Lcdrdy S1D13705 Generic #2 Pin Names Generic #2 Interface Mode VR4102/VR4111 to S1D13705 Interface Busclk BS# RD/WR# S1D13705 Hardware Configuration See Host Bus Selection table below NEC VR4102/VR4111 Configuration Software References Santa Clara California Tel 800 Fax 800 NEC Electronics IncNEC Electronics Inc. U.S.A This page Left Blank Interfacing to the PC Card Bus Document Number X27A-G-009-02 This page Left Blank S1D13705 Bus Interface Memory Access CyclesInterfacing to the PC Card Bus PC Card to S1D13705 Interface This page Left Blank PC Card Read Cycle This page Left Blank Introduction PC Card System Bus Memory Access CyclesInterfacing to the PC Card Bus PC Card Overview PC Card Read Cycle S1D13705 Bus Interface Generic #2 Interface Mode PC Card to S1D13705 Interface Hardware Connections Signal Low High Register/Memory Mapping Software PC Card Pcmcia Standard March PC Card Standard Pcmcia Interfacing to the Motorola MPC821 Microprocessor Document Number X27A-G-010-02 X27A-G-010-02 Issue Date 01/02/13 MPC821 to S1D13705 Interface Host Bus Interface Modes Generic #1 Host Bus Interface ModeIntroduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction MPC821 Bus Overview Interfacing to the MPC821MPC8xx System Bus Power PC Memory Read Cycle Normal Non-Burst Bus Transactions Power PC Memory Write Cycle Burst Cycles Memory Controller Module General-Purpose Chip Select Module Gpcm User-Programmable Machine UPM Host Bus Interface Modes Generic #1 Host Bus Interface Mode MPC821 to S1D13705 Interface Typical Implementation of MPC821 to S1D13705 Interface MPC821ADS Evaluation Board Hardware Connections List of Connections from MPC821ADS to S1D13705 P12-A3, P12-B3, P12-A4, P12-B4 P6-A14 WE0#P12-A1, P12-B1, P12-A2, P12-B2 P12-A5, P12-B5, P12-A6, P12-B6 Configuration Settings MPC821 Chip Select Configuration Test Software 1FFE0 Epson Research and Development Software Motorola Inc. Literature Distribution Center 800 Epson LCD/CRT Controllers S1D13705 Motorola MPC821 Processor Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X27A-G-011-02 X27A-G-011-02 Issue Date 01/02/13 Epson LCD Controllers S1D13705 Motorola MCF5307 Processor Host Bus Pin Connection Generic #1 Interface ModeIntroduction Interfacing to the MCF5307 This page Left Blank List of Tables This page Left Blank Introduction Interfacing to the MCF5307 MCF5307 System Bus MCF5307 Memory Read Cycle Chip-Select Module S1D13705 Bus Interface Generic #1 Interface Mode MCF5307 To S1D13705 Interface Typical Implementation of MCF5307 to S1D13705 Interface Little Endian Big Endian = configuration for MFC5307 support MCF5307 Chip Select Configuration Software References Motorola MCF5307 Processor Interfacing to the Philips Mips PR31500/PR31700 Processor Document Number X27A-G-012-02 This page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 to PR31500/PR31700 Direct Connection This page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13705 Host Bus Interface Generic #1 Interface Mode Generic #2 Interface Mode Direct Connection to the Philips PR31500/PR31700 S1D13705 to PR31500/PR31700 Direct Connection Memory Mapping and Aliasing S1D13705 Configuration and Pin Mapping Using the ITE IT8368E PC Card Buffer S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 S1D13705 aliased 128 times 0900 0000h S1D13705 Configuration Software Philips Mips PR31500/PR31700 Processor Philips Semiconductors S5U13704/5 TMPR3912/22U CPU Module Document Number X00A-G-004-02 S5U13704/5 TMPR3912/22U CPU Module Table of Contents This page Left Blank List of Tables List of Figures This page Left Blank General Description S1D13704/5 Bus Interface Bus Interface Modes Generic #2 Interface Mode TMPR3912/22U and S1D13704/5 Interface Hardware Connections Memory Mapping and Aliasing S1D13704/5 Configuration and Pin Mapping= configuration for Toshiba TMPR3912/22U host bus interface S1D13704/5 Generic #2 Interface Pin Mapping CPU Module Description Clock Signals BusclkLCD Connectors 1 50-pin LCD Module Connector, J3 Clki Lcdpwr Polarity Standard Epson LCD Connector, J4LCD Controller 1 S1D13704 vs. S1D13705 3 S1D13704\75 Chip Select This page Left Blank Interfacing to the NEC VR4181A Microprocessor Document Number X27A-G-013-02 X27A-G-013-02 VR4181A to S1D13705 Interface NEC VR4181A System Bus Overview LCD Memory Access SignalsIntroduction Interfacing to the NEC VR4181A This page Left Blank Typical Implementation of VR4181A to S1D13705 Interface This page Left Blank Introduction Interfacing to the NEC VR4181A NEC VR4181A System Bus LCD Memory Access Signals BHE# Generic #2 Interface Mode VR4181A to S1D13705 Interface Typical Implementation of VR4181A to S1D13705 Interface S1D13705 Hardware Configuration NEC VR4181A Configuration Software References Technical Support This page Left Blank Interfacing to an 8-bit Processor Document Number X27A-G-015-01 X27A-G-015-01 Issue Date 01/12/20 Bit Processor to S1D13705 Interface Interfacing to an 8-bit ProcessorGeneric 8-bit Processor System Bus Epson LCD/CRT Controllers S1D13705 This page Left Blank List of Tables This page Left Blank Introduction Interfacing to an 8-bit Processor Generic 8-bit Processor System Bus S1D13705 Generic #2 Description Pin Names Generic #2 Interface Mode Bit Processor to S1D13705 Interface = required configuration for this application Little Endian Big Endian Software References Technical Support This page Left Blank