Epson S1D13705 4 Interfacing to the MC68VZ328

Page 22 Epson Research and Development

Vancouver Design Center

S1D13705 Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors

X27A-G-007-04 Issue Date: 01/02/13

4 Interfacing to the MC68VZ328

The MC68VZ328 is Motorola’s third generation Dragonball microprocessor. The Dragon-

ballVZ is an integrated controller for handheld products, based upon the FLX68000 micro -

processor core with an external 24-bit address bus and 16-bit data bus. The DragonballVZ

differs from its predecessor mainly in that it has increased speed, and support for S DRAM

has been added to the DRAM controller. The bus interface consists of all the standard

MC68000 bus interface signals except AS, plus some new signals intended to simpli fy th e

task of interfacing to typical memory and peripheral devices. The 68000 signals are multi-

plexed with IrDA, SPI and LCD controller signals.

The MC68000 bus control signals are well documented in Motorola’s user manuals, and

will not be described here. A brief summary of the new signals appears below:

• Output Enable (OE) is asserted when a read cycle is in process; it is intended to connect

to the output enable control of a typical static RAM, EPROM, or Flash EPROM device.

• Upper Write Enable and Lower Write Enable (UWE / L WE) are asserted during

memory write cycles for the upper and lower bytes of the 16-bit data bus; they may be

directly connected to the write enable inputs of a typical memory device.

The S1D13705 implements the MC68000 bus interface using its MC68K #1 mode. This

mode may be used to interface the S1D13705 to the DragonballVZ if extern al logi c is us ed

to generate AS. The Generic #1 interface mode on the S1D13705 is also well suited to

interface to the MC68VZ328.

The MC68VZ328 can generate up to 8 chip select outputs, organized into four groups, “A ”

through “D”.

Each chip select group has a common base address register and address mask register, to

set the base address and block size of the entire group. In addition, e ach chip select within

a group has its own address compare and address mask register, to activate the chip select

for a subset of the group’s address block. Finally, each chip select may be individually

programmed to control an 8 or 16-bit device, and each may be individually programmed to

generate from 0 through 6 wait states internally, or allow the memory or peripheral device

to terminate the cycle externally through use of the standard MC68000 DTACK signal.

Groups A and B are used to control ROM, SRAM, and Flash memory devices and have a

block size of 128K bytes to 16M bytes. Chip select A0 is active immediately after reset and

is a global chip-select so it is typically used to control a boot EPROM device. This chip

select ceases to decode globally once this chip-select’s registers are programmed. Groups

C and D are special in that they can also control DRAM interfaces. These last two groups

have block size of 32K bytes to 4M bytes.