AT&T AT&T manual Memory Circuit Pack ZTN81 or ZTN127, Timing and Control Logic Circuit

ROM Select: information.

Memory Circuit Pack (ZTN81 or ZTN127)

The Memory Circuit Pack provides for the storage of software associated with system operation. This software includes call and administration processing, and other related programs. The circuit pack is powered from the backplane by +5 volts. Each system must include one Memory Circuit Pack. The Memory Circuit Pack circuitry (Figure 3-3)includes:

● Address and data buffers

●ROM array

●ROM select

●Timing and control logic

●Built-in TDM bus termination resistors.

Address and Data Buffers: The address and data buffers interface the Memory Circuit Pack to the address and data lines on the front plane.

ROM Array: The memory array consists of 16 ROM devices of 32K, 8 bit bytes each, for a total capacity of 512K ROM. The ROMs are organized into pairs allowing the Call Processor to access 16 bit words.

T h e m e m o r y s e l e c t s t h e p r o p e r p a i r o f R O M s a c c o r d i n g t o a d d r e s s

Timing and Control Logic Circuit:	C o n t r o l s t h e	a c c e s s	s p e e d o f	t h e R O M ( n o w a i t
states) by returning a Data Transfer	Acknowledge	signal at	the proper	time.

Bus Terminators: These resistors are required for proper operation of the TDM bus. The Memory Circuit Pack provides the proper termination for one end of the bus, and a plug-in TDM bus termination circuit card (plugs into cabinet backplane) is used to terminate the other end. For this reason, the Memory Circuit Pack must always be located in slot #l of Cabinet 1.

/

FRONT PANEL

MEMORY BUS

(TO CALL

PROCESSOR

CIRCUIT

PACK )

\

ADDRESS

AND

DATA BUFFERS

ROM

SELECT

TIMING

AND

CONTROL

TERMINATOR

RESISTORS

ROM

ARRAY

\

TO

TDM

BUS

/

Figure 3-3. Memory (ZTN81 or ZTN127) Circuitry

3 - 5