Intel MPCBL0010 manual 100, 101, 102, 103, 104, 106, 107, 108, 109, 110, 111, 112, 113, 105, 114

		MPCBL0010—
54	OS Load Timeout Timer Sub-Menu	85
55	Security Menu	85
56	Chipset Menu	86
57	Northbridge Chipset Configuration	86
58	Spread Spectrum Clocking Mode Configuration	87
59	Exit Menu	87
60	BIOS Error Messages	89
61	Bootblock Initialization Code Checkpoints	90
62	POST Code Checkpoints	90
63	DIM Code Checkpoints	92
64	ACPI Runtime Checkpoints	92
65	PCI Configuration Map	93
66	FPGA Register Legend	95
67	FPGA Register Overview	96
68	POST Codes 00:80h	96
69	Extended POST Codes 0081h	96
70	FPGA Version 0A00h	97
71	Debug LED 0A01h	97
72	FWUM 0A02h	98
73	Development Features 0A04h	98
74	Telecom Clock Register 0 0A08h	99
75	Telecom Clock Register 1 0A09h	100
76	Telecom Clock Register 2 0A0Ah	100
77	Telecom Clock Register 3 0A0Bh	101
78	Transmission Frequency Selection	101
79	Telecom Clock Register 4 0A0Ch	101
80	Telecom Clock Register 5 0A0Dh	102
81	Telecom Clock Register 6 0A0Eh	102
82	Telecom Clock Register 7 0A0Fh	103
83	IPMC Register Legend	103
84	SBC Control 00h	104
85	SBC Status 01h	106
86	POST Code Low 02h	106
87	POST Code High 03h	106
88	LED Color Control 06h	106
89	LED Control 07h	106
90	AdvancedMC B1 Control & Status 10h	107
91	AdvancedMC B1 Control & Status 11h	107
92	AMC B2 Control & Status 12h	108
93	AdvancedMC B2 Control & Status 13h	108
94	CPU 0 VIDs 18h	109
95	CPU 0 Status 19h	109
96	ADC Grab Control 20h	109
97	ADC1 and ADC2 Grab Data 21-22h	110
98	Fabric Control 1 24h	110
99	Fabric Control 2 25h	111
100	Reset Source 27h	111
101	Firmware Hub Control 28h	111
102	Reset Events 29h	111
103	Crosspoint Switch Control 2Ah	112
104	Crosspoint Switch Ports Register	113
105	Crosspoint Switch Data 2Bh	113
106	Miscellaneous Controls and Status 2Dh	113
107	IPMC POST Codes FEh	113
108	Version FFh	114
Intel NetStructure® MPCBL0010 Single Board Computer
Technical Product Specification		October 2006
10		Order Number: 304120