MPCBL0010
Note: Use this bit for testing only. In normal operation, leave this bit set to 0. Otherwise, the MPCBL0010 SBC will not be compliant with the AdvancedTCA* specification.
| RESET: Hardware reset of the PLL |
|
|
|
|
|
| |||
Table 80. | Telecom Clock Register 5 0A0Dh |
|
|
|
|
|
| |||
|
|
|
|
|
|
|
|
|
|
|
| Address | Action | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|
|
|
|
|
|
|
|
|
|
|
|
| Read | PCB |
|
|
| Version |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 0xA0D | Write | NU |
|
|
| NU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| Reset | PCB |
|
|
| Version |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PCB: Set to 1 to indicate that the compilation switch is properly set in the source code and that the PLD is compiled for PCB revision 1.
VERSION: PLD code version. Values:
PCB&Version: FF: indicates a test PLD to make a clock generator
PCB&Version: FE: indicates a test PLD used during manufacturing tests
Table 81. | Telecom Clock Register 6 0A0Eh |
|
|
|
|
|
| |||
|
|
|
|
|
|
|
|
|
|
|
| Address | Action | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|
|
|
|
|
|
|
|
|
|
|
|
| Read | UNLOCK1 | UNLOCK | HLDOVR | HLDOVR | SEC10 | SEC01 | PRI10 | PRI01 |
|
| 0 | 01 | 10 | 01 | |||||
|
|
|
|
|
|
| ||||
| 0xA0E |
|
|
|
|
|
|
|
|
|
| Write | NU | NU | NU | NU | NU | NU | NU | NU | |
|
| |||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| Reset | X | X | X | X | X | X | X | X |
|
|
|
|
|
|
|
|
|
|
|
PRI01: Bit PRI_LOS in telecom clock register 2 switched from 0 to 1
PRI10: Bit PRI_LOS in telecom clock register 2 switched from 1 to 0
SEC01: Bit SEC_LOS in telecom clock register 2 switched from 0 to 1
SEC10: Bit SEC_LOS in telecom clock register 2 switched from 1 to 0
HLDOVR01: Bit HOLDOVER in telecom clock register 2 switched from 0 to 1
HLDOVR10: Bit HOLDOVER in telecom clock register 2 switched from 1 to 0
UNLOCK01: Bit UNLOCK in telecom clock register 2 switched from 0 to 1
UNLOCK10: Bit UNLOCK in telecom clock register 2 switched from 1 to 0
This register reports changes since the last time it was read. A legacy ISA interrupt is generated when any of these bits are set. The actual interrupt used is assigned by the BIOS at boot time and can be read from telecom clock register 7.
Reading this register clears all bits that were '1' prior to reading. Bits that turned to '1' during the reading are not affected.
Intel NetStructure® MPCBL0010 Single Board Computer |
|
Technical Product Specification | October 2006 |
102 | Order Number: 304120 |
