Intel NetStructure® MPCBL0010 Single Board Computer
October 2006 Technical Product Specification
Order Number: 304120 113
Addressing—MPCBL0010 SBC
D[3..0]: Data to write in the crosspoint chip. (See the crosspoint control register.)
Busy: When set, the interface is busy; wait for this bit to be 0 before writing in
registers 2A-2Bh. The time for the complete transfer is less than 8 ms.
SwHw: When set, the reset switch performs a hardware reset independent of the
IPMC. When cleared, the IPMC handles the hard/warm reset.
JMPO: Status of jumper 0: 0 = In, 1 = Out
JMP1: Status of jumper 1: 0 = In, 1 = Out
POST Codes: POST codes are captured in this register as they are written. The content
of this register is serialized and transmitted off-board to a display module if bit IPOST
(register 2Ah) is set. Otherwise, the register is functional but the display module will
show the CPU POST codes.
Table 104. Crosspoint Switch Ports Register
Chip Port Input Signal Source Port Output Signal Designation
0
A0 AMC B1 port 0 Y0 AMC B1 port 0
A1 AMC B2 port 0 Y1 AMC B2 port 0
A2 Fabric Channel 1 port 0 Y2 Fabric Channel 1 port 0
A3 Fabric Channel 1 port 1 Y3 Fabric Channel 1 port 1
1
A0 AMC B1 port 1 Y0 AMC B1 port 1
A1 AMC B2 port 1 Y1 AMC B2 port 1
A2 Fabric Channel 2 port 0 Y2 Fabric Channel 2 port 0
A3 Fabric Channel 2 port 1 Y3 Fabric Channel 2 port 1
Table 105. Crosspoint Switch Data 2Bh
Address Action D7 D6 D5 D4 D3 D2 D1 D0
2Bh
Read Busy NU NU NU D3 D2 D1 D0
Write N U NU NU NU D3 D2 D1 D 0
PowerUp NU NU NU NU 0 0 0 0
Table 106. Miscellaneous Controls and Status 2Dh
Address Action D7 D6 D5 D4 D3 D2 D1 D0
2Dh
Read NU NU NU SwHw NU NU JMP1 JMP0
Write N U NU NU SwHw N U NU NU NU
PowerUp NU NU NU 1 NU NU NU NU
Table 107. IPMC POST Codes FEh
Address Action D7 D6 D5 D4 D3 D2 D1 D0
FEh
Read POST Codes
Write POST Codes
PowerUp 00h