System Management Sub-Menu, Apic Acpi SCI IRQ

BIOS Setup—MPCBL0010 SBC

Table 35. Chipset ACPI Configuration Sub-Menu

Feature	Options	Description

APIC ACPI SCI IRQ	Disabled	Enable/Disable APIC ACPI SCI interrupt.
APIC ACPI SCI IRQ	Enabled	Enable/Disable APIC ACPI SCI interrupt.
	Enabled

Note: Bold text indicates default setting.

7.3.5System Management Sub-Menu

To access this sub-menu, select Advanced on the menu bar, then System

Management.

Main Advanced PCIPnP Boot Security Chipset Exit

CPU Configuration

IDE Configuration

SuperIO Configuration

ACPI Configuration

System Management

Event Log Configuration

MPS Configuration

ATCA Channel Routing (PICMG)

On-board Devices Configuration

PCI Express Configuration

Remote Access Configuration

IPMI Configuration

USB Configuration

Table 36 shows the System Management information.

	Intel NetStructure® MPCBL0010 Single Board Computer
October 2006	Technical Product Specification
Order Number: 304120	71

Page 72

Image 72

Intel MPCBL0010 System Management Sub-Menu, Chipset Acpi Configuration Sub-Menu, Shows the System Management information

Contents

Technical Product Specification Intel NetStructure MPCBL0010 Single Board Computer Order Number Contents Weight 1.11.2 1.3 10.8 OEM Ipmi Commands 10.8.1 Reset Bios Flash TypePwrBtn usage Hardware Management Overview 10.8.2 13110.8.2.1 132 Component Technology 179 Warranty Information 180 16.1 177178 Safety Warnings 20.5 Chinese Safety WarningAdvancedMC Direct Connect Switch Block Diagram Warm Reset Block Diagram Supported Memory Configurations Jumper Definitions Tables 100 101102 103 Reset Bios Flash Type 131 Hot Swap LED Signals 136Reset Actions 140 SOL Configuration Reference Script Command-line Options 151 Revision History Date Revision Description Introduction Document Organization Glossary That allows your networked client computer to boot using a Intelligent Platform Management Bus. Physical two-wireSee the Low Pin Count LPC Interface specification Phase-locked Loop Feature Overview ApplicationFunctional Description Low Voltage Intel Xeon Processor Chipset Memory J10, J12 Memory Controller Hub2.2 I/O Controller Hub 2.3 64-Bit PCI Hub Timers Supported Memory Configurations4 I/O 4.1 I/O Controller Hub AdvancedMC AMC Connector J18, J19 Gigabit Ethernet4.5 10/100 Fast Ethernet 4.6 USB 6.1 FWH0 Main Bios Firmware Hubs Onboard Power Supplies 6.2 FWH1 Backup/Recovery BiosFlash ROM Backup Mechanism Power Feed Fuses Ipmc Telecom Clock AdvancedMC Direct Connect AdvancedMCA Direct Connect Switch Block Diagram AdvancedTCA Compliance Operating the Unit Jumpers Name Function with Jumper Present On Removed Off MPCBL0010 SBC AdvancedMC Filler Panels AdvancedMC Filler Panel Installing Memory Remove the cover Installing and Extracting the SBC Insert two matched pair DIMMs Chassis Installation Chassis Extraction Solid blue AdvancedMC Module Installation and Extraction Bios ConfigurationRemote Access Configuration Software Updates Bios Updates Loading\Saving Custom Bios ConfigurationBios Image Command Behavior Copying BIOS.bin from the SBC Saving BIOS.bin to the SBC Ipmc Firmware Updates Flashlnx Command Line OptionsIpmc Firmware Upgrade Using the KCS Interface Flashlnx Utility Command Line Options Digital Ground and Chassis Ground Isolated Default Digital Ground to Chassis Ground Connectivity Specifications Mechanical SpecificationsEnvironmental Specifications Board Outline Reliability Specifications Mean Time Between Failure Mtbf SpecificationsEnvironmental Assumptions General Assumptions Weight Power RequirementsPower Consumption General Notes Connectors and LEDs Connectors and LEDs-MPCBL0010 SBC Backplane Description Connectors Front Panel Front Panel Connector Assignments Front Panel Description Connectors Backplane Connectors Power Distribution Connector P10 AdvancedTCA Data Transport Connector J23 Power Distribution Connector Zone 1 P10 Pin AssignmentsPin Signal Description Data Transport Connector Zone 2 J23 AdvancedTCA Data Transport Connector J20 AdvancedTCA* Data Transport Connector Zone 2 J20 PinAlignment Blocks Pin On-Board Connectors Post Code Connector J13Extended IPT700 Debug Port Connector J25 Post Code Connector Pin Assignments Front Panel Connectors Ethernet 10/100 Debug Connector J3Ethernet 10/100 Debug Connector LED Operation Function USB Connector J4 Serial Port Connector J5 AdvancedMC* Connectors J18, J19 Serial Port Connector J5 Pin Assignments AdvancedMC* Connector Pin Assignments AdvancedMC* Connector LEDs OOS Front Panel LED Descriptions Sheet 1 OOS Post LED Codes Front Panel LED Descriptions Sheet 2 Reset Button Example Post LED Codes Bios Features Bios Flash Memory OrganizationRedundant Bios Functionality Introduction Recovering Bios Data Boot OptionsLegacy USB Support Language Support Fast Booting Systems Bios Security FeaturesCD-ROM and Network Boot Booting without Attached Devices Supervisor and User Password Functions Function Key Escape Code Equivalents Sheet 1Key Escape Sequence ESC OP ESC OQ ESC or ESC OS Function Key Escape Code Equivalents Sheet 2 ESC OW ESC OXESC OY ESC OZ Bios Setup Bios Setup Program Menu BarBios Setup Program Function Keys Main Menu Feature Options Description Bios IDAdvanced Menu Main Menu CPU Configuration Sub-Menu Advanced MenuPicmg IDE Configuration Sub-Menu Shows the sub-menu options for configuring the CPUCPU Configuration Sub-Menu Shows the IDE configuration options IDE Configuration Sub-Menu Primary IDE Master/Slave Configuration Options Shows the IDE Master/Slave configuration optionsIDE Master/Slave Sub-Menu SuperIO Configuration Sub-Menu Shows SuperIO configuration options Acpi Configuration Sub-Menu SuperIO Configuration Sub-Menu Advanced Acpi Configuration Sub-Menu Chipset Acpi Configuration Sub-MenuShows Acpi configuration options Acpi Configuration Sub-Menu Chipset Acpi Configuration Sub-Menu System Management Sub-MenuShows the System Management information Apic Acpi SCI IRQ Event Log Configuration Sub-Menu Shows event log configuration optionsSystem Management Sub-Menu PCI Express Error Masking Configuration Sub-Menu Event Log Configuration Sub-MenuPCI Express Error Masking Configuration Sub-Menu MPS Configuration Sub-Menu Shows MPS Configuration optionsMPS Configuration Sub-Menu AdvancedTCA* Channel Routing PICMG* Sub-Menu On-board Devices Configuration Sub-Menu AdvancedTCA Channel Routing Picmg Sub-Menu PCI Express* Configuration Sub-Menu Shows On-board Devices Configuration optionsOn-board Devices Configuration Sub-Menu Option ROM Configuration Options Remote Access Configuration Sub-Menu Shows PCI Express configuration optionsPCI Express* Configuration Sub-Menu Ipmi Configuration Sub-Menu Shows remote access configuration optionsRemote Access Configuration Sub-Menu Shows the Ipmi configuration options Ipmi Configuration Sub-MenuShows the LAN configuration options LAN Configuration Sub-Menu USB Configuration Sub-Menu Shows USB configuration optionsUSB Configuration Sub-Menu USB Mass Storage Device Configuration USB Mass Storage Device ConfigurationPCIPnP Menu PCIPnP Menu Boot Menu Boot Settings Configuration Sub-MenuBoot Menu Shows Boot Settings Configuration options Boot Device Priority Sub-Menu Boot Settings Configuration Sub-Menu Sheet 2Shows Boot Device Priority options Boot Device Priority Sub-Menu OS Load Timeout Timer Sub-Menu Shows OS Load Timeout Timer optionsHard Disk Drives Sub-menu Shows Hard Disk Drives options OS Load Timeout Timer Sub-Menu Shows passwords and security featuresSecurity Menu Chipset Menu Northbridge Configuration Sub-Menu Describes the sub-menus used to select chipset featuresNorthbridge Chipset Configuration Chipset Menu Spread Spectrum Clocking Mode Sub-Menu Spread Spectrum Clocking Mode ConfigurationExit Menu Exit Menu Exit Menu Error Messages Bios Error MessagesBios Error Messages Cmos Checksum BAD Clear Cmos Jumper enabled Bootblock Initialization Code Checkpoints Post Code CheckpointsCheckpoint Description Smram Early CPU Init Exit DIM Code Checkpoints Acpi Runtime Checkpoints PCI Configuration Map PCI Configuration MapAddressing Lists the PCI devices and the bus on which they reside AMC B2 AMC B1 Symbol Description Fpga RegistersFpga Register Legend Fpga Register Overview Post Codes 0080hExtended Post Codes 0081h Fpga Version 0A00h Version Programmable logic versionDebug LED 0A01h Address Action Development Features 0A04h Fwum 0A02hFwum Ready Fwum Busy PCB PCB version Telecom Clock Register 0 0A08h Hwmode Holos MS2 MS1 Refalign FCS E3DS3 Telecom Clock Register 1 0A09h Telecom Clock Register 2 0A0Ah Telecom Clock Register 3 0A0Bh Transmission Frequency SelectionTelecom Clock Register 4 0A0Ch TXREFxSEL2..0 Transmission Clock Frequency 0xA0D Write Reset Telecom Clock Register 6 0A0EhUnlock Hldovr SEC10 SEC01 PRI10 PRI01 Ipmc Addresses Telecom Clock Register 7 0A0FhIpmc Register Legend Address Function SBC Control 00h Ltype Ltest Uart BrstHT0 PwrBtn usage SBC Status 01h Post Code Low 02hPost Code High 03h LED Color Control 06h AdvancedMC B1 Control & Status 10h AdvancedMC B1 Control & Status 11h AMC B2 Control & Status 12h AdvancedMC B2 Control & Status 13h CPU 0 VIDs 18h ADC Grab Control 20hVID5 VID4 VID3 VID2 VID1 VID0 Mcerr HOT Trip VTT Ierr ADC1 and ADC2 Grab Data 21-22h Fabric Control 1 24hPCB 3VOC Reset Source 27h Default configuration connects FWH0 and FWH1 to the ICHReset Events 29h Fabric Control 2 25h Crosspoint Switch Control 2Ah Crosspoint Switch Ports Register Crosspoint Switch Data 2BhMiscellaneous Controls and Status 2Dh Ipmc Post Codes FEh Address Action FFh Read Reserved Version Write PowerUp Version FFh Hardware Management Overview Intelligent Platform Management Controller Ipmc Ipmc Block Diagram Sensor Data Record SDR Hardware Sensors Sheet 1Green to Red State M1 Hardware Sensors Sheet 2 Hardware Sensors Sheet 3 Hardware Sensors Sheet 4 OEM Sensor TypesOEM Name OEM Number Description System Event Log SEL OEM Event/Reading TypeSEL Events Supported Sheet 1 Sensor Sensor Type Specific Event Description Code SEL Events Supported Sheet 2 PCI SerrPCI Perr SO/GO SEL Events Supported Sheet 3 When name is FIA FRU Initialization SEL Events Supported Sheet 4 SEL Events Supported Sheet 5 Sensor Sensor Type Specific Event Description Code OffsetOEM Ipmb Link Sensor Field Replaceable Unit FRU InformationVariable Size Data Type Bytes ASC-II Customizable FRU Area LinuxCustFru Utility UsageFRU Customer Area Example 1. Input File Seecommon AB AC AD AE AF OEM Ipmi Commands Keying Reset Bios Flash Type Reset Bios Flash TypeBoard Device Channel Port Selection Identifiers Channel Port Selection Identifiers SetBoardDeviceChannelPortSelection SetBoardDeviceChannelPortSelectionResponse GetBoardDeviceChannelPortSelection GetBoardDevicePossibleSelectionGetBoardDeviceChannelPortSelection GetBoardDevicePossibleSelection Set Control State Get Control StateControls Identifier Table Set Control State Hot Swap Process Controls IdentifierControl Description Control Number FWH Hot Swap LED Signals AdvancedMC Module ActivationHot Swap LED LED Status Meaning Temperature and Voltage Sensors Pre-Defined Resources for AdvancedMC Modules Sensors and Thresholds Version SDR System Firmware Progress Post Error System Acpi Power StateProcessor Events Dimm Memory Events Reset Reset ActionsReset Action System Function Memory Status Ipmb Link Sensor Warm Reset Hard Reset Ipmc Firmware Code Ipmc Firmware Code Process MPCBL0010 SBC-Hardware Management Overview Serial Over LAN SOL ReferencesSOL Architecture SOL Implementation SOL Block Diagram Theory of Operation Architectural ComponentsFront Panel Serial Port or Rear Transition Module Serial Over LAN Reference Configuration Script Serial Over LAN Client Configuring the Blade for SOL Supported Usage Model SOL Configuration Reference Script referencecfg Default BehaviorReference Script referencecfg SOL User Information Command Line Options SOL Configuration Reference Script Command-line OptionsSOL Parameters Channel Parameters Setting up a Serial Over LAN Session Target Blade SetupBios Configuration Operating System Configuration Change the serial parameter to read Change the kernel line to read For Rhel Sbcutils RPM Installation Execute the referencecfg Script Execute this command to configure SOL on the target blade Script executed on the Intel CMM Client Blade Setup Configure the Ethernet PortExecute this command to restart the network For RedHat* Rhel Configure IP address of the Ethernet port Installing ipmitool Checking SOL ConfigurationStart an SOL Session Ending an SOL Session OEM Operating Systems for SOL Client ipmitool Block Diagram of the Telecom Clock Telecom Clock Interface Description Function Description Recovered Clock Selection ConfigurationAlarm Handling Operational Configuration Enable/Disable Transmission Clock Telecom Clock APIModule Transmission Frequency Selection Name Used For Value Recovered Clock Automatic SwitchoverAutomatic Switchover Mode Automatic Switchover Values Select Reference Clock Reference Frequency for PLLPrimary/Secondary Redundant Clock PLL Operating Mode Hardware ResetCorner Frequency Reference Clock Alignment Read Alarm States Hardware Reset ValuesAlarm State Values Read New Events Read the Current Reference Clock Sysfs InterfaceReference Clock Values Telecom Clock API Function Mapping for the sysfs Interface Telecom Clock Registers 80hA10-A1Fh October Technical Product Specification Order Number 171 DRVCLKB1 DRVCLKA1 DRVCLKB0 DRVCLKA0 Addres Action UNLOCK10 UNLOCK01 HLDOVR10 HLDOVR01 SEC10 SEC01 PRI10 PRI01 October Technical Product Specification Order Number 175 FPGA/PLD Serial Link Bit Definition Bit Write Read Maintenance DiagnosticsSupervision In-Target Probe ITP Power vs. Flow Rate Thermals Component Technology Warranty Information Returning a Defective Product RMAFor the Americas For Europe, Middle East, and Africa Emea For Asia and Pacific ApacLimitation of Liability and Remedies MPCBL0010 SBC-Warranty Information Technical Support and Return for Service Assistance Customer SupportCustomer Support Sales Assistance Certifications Vcci Cisprzz Agency Information-Class B North America FCC Class BJapan Vcci Class B Korean Class B Australia, New Zealand Safety Warnings Mesures de Sécurité Sicherheitshinweise Norme di Sicurezza Instrucciones de Seguridad Chinese Safety Warning Appendix a Reference Documents MPCBL0010 SBC-Reference Documents Appendix B List of Supported Commands Ipmi v1.5 and Picmg Ipmi 1.5 Supported Commands Sheet 1 Ipmi 1.5 Supported Commands Sheet 2 FRU Device Commands NetFn Picmg 3.0 Ipmi Supported Commands Command NetFn Interface

Intel MPCBL0010 manual System Management Sub-Menu, Chipset Acpi Configuration Sub-Menu

Models: Intel NetStructure Single Board Computer MPCBL0010

Table 35. Chipset ACPI Configuration Sub-Menu

Feature

APIC ACPI SCI IRQ

Disabled

7.3.5System Management Sub-Menu

Management.

System Management

Table 36 shows the System Management information.