Intel MPCBL0010 manual Memory J10, J12, Memory Controller Hub, 2.2 I/O Controller Hub

Feature Overview—MPCBL0010 SBC

• Intel® 6700PXH 64-bit PCI Hub

A brief overview is provided here and detailed component information can be found in each device’s respective documentation.

2.2.2.1Memory Controller Hub

The architecture of the Intel® E7520 MCH provides the performance and feature set required for performance servers, with configuration options facilitating optimization of the platform for workloads characteristic of communication, presentation, storage, performance computation, or database applications. To accomplish this optimization, the MCH has numerous Reliability, Availability, Serviceability, Usability, and Manageability (RASUM) features on multiple interfaces.

The front side bus supports a base system bus frequency of 200 MHz. The address and request interface is double-pumped to 400 MHz while the 64-bit data interface (+ parity) is quad-pumped to 800 MHz. This arrangement provides a matched system bus address and data bandwidths of 6.4 GBytes/s. The MCH provides an integrated memory controller for direct connection to registered DDR2-400 memory.

The MCH is compatible with PCI Express* Interface Specification, Rev 1.0a. The MCH provides three configurable x8 PCI Express interfaces, each with a max theoretical bandwidth of 4 GBytes. The MCH supports PCI Express Hot Swap. The MCH is a root class component as defined in the PCI Express Interface Specification, Rev1.0a.

The MCH connects with the 6300ESB ICH through a dedicated Hub Interface 1.5 that supports a peak bandwidth of 266 MByte/s using a x4 base clock of 66 MHz.

2.2.2.2I/O Controller Hub

The Intel®6300ESB ICH provides legacy function support similar to that of previous ICH-family devices, but with extensions in Serial ATA technology and 32-bit/33 MHz PCI-X support. The 6300ESB ICH also includes integrated USB 2.0 and USB 1.0 support, an LPC interface, a system management interface, a power management interface, integrated IOxAPIC and 8259 interrupt controllers, and an integrated DMA controller.

2.2.2.364-Bit PCI Hub

The Intel® 6700PXH PCI Hub provides the connection between a PCI Express interface and two independent PCI bus interfaces configurable for standard PCI 2.3 protocol, as well as the enhanced high-frequency PCI-X 1.0b protocol. The 6700PXH provides configurable support for 32- or 64-bit PCI devices.

The MPCBL0010 SBC implements four gigabit Ethernet interfaces by means of two high-speed Intel® 82546GB Dual Port Gigabit Ethernet controllers. These controllers are connected to the 6700PXH through a shared PCI-X interface. One controller is connected to the base interface and the other to the fabric interface on the AdvancedTCA backplane to support PICMG 3.0 and 3.1 specifications.

2.2.3Memory (J10, J12)

The memory subsystem is designed to support Double Data Rate2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the E7520 MCH. The MCH provides two independent DDR channels, which support DDR2-400 DIMMs. The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s) with DDR2-400. The two DDR2 channels from the MCH operate in lock step; the effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for DDR2 400.

	Intel NetStructure® MPCBL0010 Single Board Computer
October 2006	Technical Product Specification
Order Number: 304120	17