MPCBL0010 SBC—BIOS Setup
Intel NetStructure® MPCBL0010 Single Board Computer
Technical Product Specification October 2006
86 Order Number: 304120
Tabl e 56 describes the sub-menus used to select chipset features.
7.7.1 Northbridge Configuration Sub-Menu
To access this menu, select Chipset from the menu bar and then NorthBridge
Configuration.
Tabl e 57 shows the sub-menu used for configuring the Northbridge options.
Main Advanced PCIPnP Boot Security Chipset Exit
NorthBridge Configuration
Spread Spectrum Clocking
Mode
Table 56. Chipset Menu
Feature Options Description
Northbridge
Configuration Select to display sub-menu Set Northbridge options.
Spread Spectrum
Clocking Mode Enabled
Disabled Enables / Disables Spread Spectrum
Clocking for EMI control.
Note: Bold text indicates default setting.
Main Advanced PCIPnP Boot Security Chipset Exit
NorthBridge Configuration
Spread Spectrum Clocking
Mode
Table 57. Northbridge Chipset Configuration
Feature Options Description
Memory Remap Feature Disabled
Enabled Enables / Disables remapping of overlapped
PCI memory above the total physical limit.
Memory Mirroring/Sparring Disabled Disables Memory Mirroring.
DMA Controller Disabled
Enabled Enable / Disable DMA Controller.
DDR2 Refresh
Auto
7.8uS
3.9uS
Specifies DDR2 refresh rate. A higher refresh
rate (7.8uS) may be required when operating
in high temperature environments with certain
types of DIMMs. The default Auto setting uses
the memory SEEPROM (SPD) byte 12 Refresh
Rate/Type to determine the appropriate setting.
Note: Bold text indicates default setting.