SBC Status 01h | Intel Intel NetStructure Single Board Computer

MPCBL0010 SBC—Addressing

Table 85.	SBC Status 01h

	Address	Action	D7	D6	D5	D4	D3	D2	D1	D0

		Read	Vcore	1.2V	1.5V	1.8V	2.5V	3.3V	5V	12V

	01h	Write	NU	NU	NU	NU	NU	NU	NU	NU

		PowerUp	NU	NU	NU	NU	NU	NU	NU	NU

Table 86. POST Code Low 02h

	Address	Action		D7	D6	D5	D4	D3	D2	D1	D0

		Read		Last access to I/O 80 in the BIOS address space

	02h	Write		NU	NU	NU	NU	NU	NU	NU	NU

		PowerUp		NU	NU	NU	NU	NU	NU	NU	NU

Table 87.	POST Code High 03h

	Address	Action	D7	D6	D5	D4	D3	D2	D1	D0

		Read	Last access to I/O 81 in the BIOS address space

	03h	Write	NU	NU	NU	NU	NU	NU	NU	NU

		PowerUp	NU	NU	NU	NU	NU	NU	NU	NU

Table 88.	LED Color Control 06h

	Address	Action	D7	D6	D5		D4	D3	D2	D1	D0

		Read	U2COL1	U2COL0	U1COL1		U1COL0	L2COL1	L2COL0	L1COL1	L1COL0

	06h	Write	U2COL1	U2COL0	U1COL1		U1COL0	L2COL1	L2COL0	L1COL1	L1COL0

		PowerUp	0	0	0		0	0	0	0	0

	L1COL[1:0]: ATCA LED 1 color control: 00					= amber, 10 = red, others = off
	L2COL[1:0]: ATCA LED 2 color control: 00					= amber, 10 = red, 01 = green, others =
	off

U1COL[1:0]: User LED 1 color control: 00 = amber, 10 = red, 01 = green, others =off

U2COL[1:0]: User LED 1 color control: 00 = amber, 10 = red, 01= green, others = off

Table 89. LED Control 07h

Address	Action	D7	D6	D5	D4	D3	D2	D1	D0

	Read	0LED1		ULED2	ULED1	LED3	LED2	LED1	LED0

07h	Write	0LED1		ULED2	ULED1	LED3	LED2	LED1	LED0

	PowerUp	0		0	0	0	0	0	1

LED0: Standard ATCA0 LED control: Hotswap LED, color is blue

LED1: Standard ATCA1 LED control: Out of service LED, color from LED color control register. This bit only works if bit OLED1 is set

LED2: Standard ATCA2 LED control: Health LED, color from LED color control register

Intel NetStructure® MPCBL0010 Single Board Computer
Technical Product Specification	October 2006
106	Order Number: 304120

Image 107

Intel Intel NetStructure Single Board Computer SBC Status 01h, Post Code Low 02h, Post Code High 03h, LED Control 07h

Contents

Intel NetStructure MPCBL0010 Single Board Computer Technical Product Specification Order Number Contents 1.3 Weight1.1 1.2 Hardware Management Overview 10.8 OEM Ipmi Commands10.8.1 Reset Bios Flash Type PwrBtn usage 132 10.8.2131 10.8.2.1 178 Component Technology 179 Warranty Information 180 16.1177 Warm Reset Block Diagram Safety Warnings20.5 Chinese Safety Warning AdvancedMC Direct Connect Switch Block Diagram Tables Supported Memory Configurations Jumper Definitions 103 100101 102 SOL Configuration Reference Script Command-line Options 151 Reset Bios Flash Type 131Hot Swap LED Signals 136 Reset Actions 140 Date Revision Description Revision History Document Organization Introduction Glossary Phase-locked Loop That allows your networked client computer to boot using aIntelligent Platform Management Bus. Physical two-wire See the Low Pin Count LPC Interface specification Functional Description Feature OverviewApplication Chipset Low Voltage Intel Xeon Processor 2.3 64-Bit PCI Hub Memory J10, J12Memory Controller Hub 2.2 I/O Controller Hub 4.1 I/O Controller Hub TimersSupported Memory Configurations 4 I/O 4.6 USB AdvancedMC AMC Connector J18, J19Gigabit Ethernet 4.5 10/100 Fast Ethernet Firmware Hubs 6.1 FWH0 Main Bios Power Feed Fuses Onboard Power Supplies6.2 FWH1 Backup/Recovery Bios Flash ROM Backup Mechanism Telecom Clock Ipmc AdvancedMC Direct Connect AdvancedTCA Compliance AdvancedMCA Direct Connect Switch Block Diagram Jumpers Operating the Unit MPCBL0010 SBC Name Function with Jumper Present On Removed Off AdvancedMC Filler Panel AdvancedMC Filler Panels Remove the cover Installing Memory Insert two matched pair DIMMs Installing and Extracting the SBC Chassis Extraction Chassis Installation Solid blue Software Updates AdvancedMC Module Installation and ExtractionBios Configuration Remote Access Configuration Bios Image Command Behavior Bios UpdatesLoading\Saving Custom Bios Configuration Saving BIOS.bin to the SBC Copying BIOS.bin from the SBC Flashlnx Utility Command Line Options Ipmc Firmware UpdatesFlashlnx Command Line Options Ipmc Firmware Upgrade Using the KCS Interface Digital Ground to Chassis Ground Connectivity Digital Ground and Chassis Ground Isolated Default Board Outline SpecificationsMechanical Specifications Environmental Specifications General Assumptions Reliability SpecificationsMean Time Between Failure Mtbf Specifications Environmental Assumptions General Notes WeightPower Requirements Power Consumption Connectors and LEDs Backplane Description Connectors Connectors and LEDs-MPCBL0010 SBC Front Panel Description Connectors Front Panel Front Panel Connector Assignments Power Distribution Connector P10 Backplane Connectors Pin Signal Description AdvancedTCA Data Transport Connector J23Power Distribution Connector Zone 1 P10 Pin Assignments Data Transport Connector Zone 2 J23 Pin AdvancedTCA Data Transport Connector J20AdvancedTCA* Data Transport Connector Zone 2 J20 Pin Alignment Blocks Post Code Connector Pin Assignments On-Board ConnectorsPost Code Connector J13 Extended IPT700 Debug Port Connector J25 Function Front Panel ConnectorsEthernet 10/100 Debug Connector J3 Ethernet 10/100 Debug Connector LED Operation Serial Port Connector J5 USB Connector J4 Serial Port Connector J5 Pin Assignments AdvancedMC* Connectors J18, J19 AdvancedMC* Connector Pin Assignments LEDs AdvancedMC* Connector OOS OOS Front Panel LED Descriptions Sheet 1 Front Panel LED Descriptions Sheet 2 Post LED Codes Example Post LED Codes Reset Button Introduction Bios FeaturesBios Flash Memory Organization Redundant Bios Functionality Language Support Recovering Bios DataBoot Options Legacy USB Support Booting without Attached Devices Fast Booting SystemsBios Security Features CD-ROM and Network Boot ESC OP ESC OQ ESC or ESC OS Supervisor and User Password FunctionsFunction Key Escape Code Equivalents Sheet 1 Key Escape Sequence ESC OZ Function Key Escape Code Equivalents Sheet 2ESC OW ESC OX ESC OY Main Menu Bios SetupBios Setup Program Menu Bar Bios Setup Program Function Keys Main Menu Feature Options DescriptionBios ID Advanced Menu Picmg CPU Configuration Sub-MenuAdvanced Menu CPU Configuration Sub-Menu IDE Configuration Sub-MenuShows the sub-menu options for configuring the CPU IDE Configuration Sub-Menu Shows the IDE configuration options IDE Master/Slave Sub-Menu Primary IDE Master/Slave Configuration OptionsShows the IDE Master/Slave configuration options Shows SuperIO configuration options SuperIO Configuration Sub-Menu SuperIO Configuration Sub-Menu Acpi Configuration Sub-Menu Acpi Configuration Sub-Menu Advanced Acpi Configuration Sub-MenuChipset Acpi Configuration Sub-Menu Shows Acpi configuration options Apic Acpi SCI IRQ Chipset Acpi Configuration Sub-MenuSystem Management Sub-Menu Shows the System Management information System Management Sub-Menu Event Log Configuration Sub-MenuShows event log configuration options PCI Express Error Masking Configuration Sub-Menu PCI Express Error Masking Configuration Sub-MenuEvent Log Configuration Sub-Menu AdvancedTCA* Channel Routing PICMG* Sub-Menu MPS Configuration Sub-MenuShows MPS Configuration options MPS Configuration Sub-Menu AdvancedTCA Channel Routing Picmg Sub-Menu On-board Devices Configuration Sub-Menu Option ROM Configuration Options PCI Express* Configuration Sub-MenuShows On-board Devices Configuration options On-board Devices Configuration Sub-Menu PCI Express* Configuration Sub-Menu Remote Access Configuration Sub-MenuShows PCI Express configuration options Remote Access Configuration Sub-Menu Ipmi Configuration Sub-MenuShows remote access configuration options LAN Configuration Sub-Menu Shows the Ipmi configuration optionsIpmi Configuration Sub-Menu Shows the LAN configuration options USB Configuration Sub-Menu USB Configuration Sub-MenuShows USB configuration options PCIPnP Menu USB Mass Storage Device ConfigurationUSB Mass Storage Device Configuration PCIPnP Menu Shows Boot Settings Configuration options Boot MenuBoot Settings Configuration Sub-Menu Boot Menu Boot Device Priority Sub-Menu Boot Device Priority Sub-MenuBoot Settings Configuration Sub-Menu Sheet 2 Shows Boot Device Priority options Shows Hard Disk Drives options OS Load Timeout Timer Sub-MenuShows OS Load Timeout Timer options Hard Disk Drives Sub-menu Chipset Menu OS Load Timeout Timer Sub-MenuShows passwords and security features Security Menu Chipset Menu Northbridge Configuration Sub-MenuDescribes the sub-menus used to select chipset features Northbridge Chipset Configuration Exit Menu Spread Spectrum Clocking Mode Sub-MenuSpread Spectrum Clocking Mode Configuration Exit Menu Exit Menu Cmos Checksum BAD Clear Cmos Jumper enabled Error MessagesBios Error Messages Bios Error Messages Smram Bootblock Initialization Code CheckpointsPost Code Checkpoints Checkpoint Description Early CPU Init Exit Acpi Runtime Checkpoints DIM Code Checkpoints Lists the PCI devices and the bus on which they reside PCI Configuration MapPCI Configuration Map Addressing AMC B2 AMC B1 Fpga Register Legend Symbol DescriptionFpga Registers Extended Post Codes 0081h Fpga Register OverviewPost Codes 0080h Address Action Fpga Version 0A00hVersion Programmable logic version Debug LED 0A01h PCB PCB version Development Features 0A04hFwum 0A02h Fwum Ready Fwum Busy Hwmode Holos MS2 MS1 Refalign FCS E3DS3 Telecom Clock Register 0 0A08h Telecom Clock Register 2 0A0Ah Telecom Clock Register 1 0A09h TXREFxSEL2..0 Transmission Clock Frequency Telecom Clock Register 3 0A0BhTransmission Frequency Selection Telecom Clock Register 4 0A0Ch Unlock Hldovr SEC10 SEC01 PRI10 PRI01 0xA0D Write ResetTelecom Clock Register 6 0A0Eh Address Function Ipmc AddressesTelecom Clock Register 7 0A0Fh Ipmc Register Legend HT0 SBC Control 00hLtype Ltest Uart Brst PwrBtn usage LED Color Control 06h SBC Status 01hPost Code Low 02h Post Code High 03h AdvancedMC B1 Control & Status 11h AdvancedMC B1 Control & Status 10h AdvancedMC B2 Control & Status 13h AMC B2 Control & Status 12h Mcerr HOT Trip VTT Ierr CPU 0 VIDs 18hADC Grab Control 20h VID5 VID4 VID3 VID2 VID1 VID0 PCB 3VOC ADC1 and ADC2 Grab Data 21-22hFabric Control 1 24h Fabric Control 2 25h Reset Source 27hDefault configuration connects FWH0 and FWH1 to the ICH Reset Events 29h Crosspoint Switch Control 2Ah Ipmc Post Codes FEh Crosspoint Switch Ports RegisterCrosspoint Switch Data 2Bh Miscellaneous Controls and Status 2Dh Version FFh Address Action FFh Read Reserved Version Write PowerUp Intelligent Platform Management Controller Ipmc Hardware Management Overview Ipmc Block Diagram State M1 Sensor Data Record SDRHardware Sensors Sheet 1 Green to Red Hardware Sensors Sheet 2 Hardware Sensors Sheet 3 OEM Name OEM Number Description Hardware Sensors Sheet 4OEM Sensor Types Sensor Sensor Type Specific Event Description Code System Event Log SELOEM Event/Reading Type SEL Events Supported Sheet 1 SO/GO SEL Events Supported Sheet 2PCI Serr PCI Perr SEL Events Supported Sheet 3 SEL Events Supported Sheet 4 When name is FIA FRU Initialization OEM SEL Events Supported Sheet 5Sensor Sensor Type Specific Event Description Code Offset ASC-II Ipmb Link SensorField Replaceable Unit FRU Information Variable Size Data Type Bytes FRU Customer Area Customizable FRU AreaLinuxCustFru Utility Usage Seecommon Example 1. Input File AB AC AD AE AF Keying OEM Ipmi Commands Channel Port Selection Identifiers Reset Bios Flash TypeReset Bios Flash Type Board Device Channel Port Selection Identifiers Response SetBoardDeviceChannelPortSelectionSetBoardDeviceChannelPortSelection GetBoardDevicePossibleSelection GetBoardDeviceChannelPortSelectionGetBoardDevicePossibleSelection GetBoardDeviceChannelPortSelection Set Control State Set Control StateGet Control State Controls Identifier Table FWH Hot Swap ProcessControls Identifier Control Description Control Number LED Status Meaning Hot Swap LED SignalsAdvancedMC Module Activation Hot Swap LED Pre-Defined Resources for AdvancedMC Modules Temperature and Voltage Sensors Sensors and Thresholds Version SDR Dimm Memory Events System Firmware Progress Post ErrorSystem Acpi Power State Processor Events Ipmb Link Sensor ResetReset Actions Reset Action System Function Memory Status Hard Reset Warm Reset Ipmc Firmware Code Ipmc Firmware Code Process MPCBL0010 SBC-Hardware Management Overview SOL Implementation Serial Over LAN SOLReferences SOL Architecture SOL Block Diagram Serial Over LAN Theory of OperationArchitectural Components Front Panel Serial Port or Rear Transition Module Serial Over LAN Client Reference Configuration Script Supported Usage Model Configuring the Blade for SOL SOL User Information SOL Configuration Reference Script referencecfgDefault Behavior Reference Script referencecfg Channel Parameters Command Line OptionsSOL Configuration Reference Script Command-line Options SOL Parameters Bios Configuration Setting up a Serial Over LAN SessionTarget Blade Setup Change the serial parameter to read Operating System Configuration For Rhel Change the kernel line to read Execute the referencecfg Script Sbcutils RPM Installation Script executed on the Intel CMM Execute this command to configure SOL on the target blade For RedHat* Rhel Configure IP address of the Ethernet port Client Blade SetupConfigure the Ethernet Port Execute this command to restart the network Start an SOL Session Installing ipmitoolChecking SOL Configuration OEM Ending an SOL Session Operating Systems for SOL Client ipmitool Telecom Clock Block Diagram of the Telecom Clock Function Description Interface Description Operational Configuration Recovered Clock SelectionConfiguration Alarm Handling Name Used For Value Enable/Disable Transmission ClockTelecom Clock API Module Transmission Frequency Selection Automatic Switchover Values Recovered ClockAutomatic Switchover Automatic Switchover Mode Primary/Secondary Redundant Clock Select Reference ClockReference Frequency for PLL Reference Clock Alignment PLL Operating ModeHardware Reset Corner Frequency Read New Events Read Alarm StatesHardware Reset Values Alarm State Values Telecom Clock API Function Mapping for the sysfs Interface Read the Current Reference ClockSysfs Interface Reference Clock Values A10-A1Fh Telecom Clock Registers80h October Technical Product Specification Order Number 171 DRVCLKB1 DRVCLKA1 DRVCLKB0 DRVCLKA0 Addres Action UNLOCK10 UNLOCK01 HLDOVR10 HLDOVR01 SEC10 SEC01 PRI10 PRI01 October Technical Product Specification Order Number 175 Bit Write Read FPGA/PLD Serial Link Bit Definition In-Target Probe ITP MaintenanceDiagnostics Supervision Thermals Power vs. Flow Rate Component Technology For the Americas Warranty InformationReturning a Defective Product RMA Limitation of Liability and Remedies For Europe, Middle East, and Africa EmeaFor Asia and Pacific Apac MPCBL0010 SBC-Warranty Information Sales Assistance Technical Support and Return for Service AssistanceCustomer Support Customer Support Vcci Cisprzz Certifications Japan Vcci Class B Agency Information-Class BNorth America FCC Class B Korean Class B Australia, New Zealand Safety Warnings Mesures de Sécurité Sicherheitshinweise Norme di Sicurezza Instrucciones de Seguridad Chinese Safety Warning Appendix a Reference Documents MPCBL0010 SBC-Reference Documents Ipmi 1.5 Supported Commands Sheet 1 Appendix B List of Supported Commands Ipmi v1.5 and Picmg FRU Device Commands NetFn Ipmi 1.5 Supported Commands Sheet 2 Command NetFn Interface Picmg 3.0 Ipmi Supported Commands